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aug, 2010 v0.12p F71858AD F71858AD hardware monitor, kbc with gpio & acpi release date: aug, 2010 version: v0.12p
aug, 2010 v0.12p F71858AD F71858AD datasheet revision history version date page revision history 0.10p 2009/6/19 - preliminary version 0.11p 2009/8/6 - add application circuit add registers & application circuits 0.12p 2010/10/5 39 add tsi/smbus address register ? index 08h please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agr ee to fully indemnify fintek for any damages resulting from such improper use or sales.
aug, 2010 v0.12p F71858AD table of content 1. general descrip tion......................................................................................................... ... 4 2. featur e li st ................................................................................................................ ........ 4 3. key spec ification........................................................................................................... ..... 6 4. pin conf iguration........................................................................................................... ..... 7 5. pin de scription ............................................................................................................. ...... 8 5.1 powe r pin.................................................................................................................. .. 8 5.2 lpc in terface .............................................................................................................. 8 5.3 keyboard c ontrolle r .................................................................................................... 9 5.4 ac pi....................................................................................................................... ..... 9 5.5 h/w m onitor .............................................................................................................. 10 6. function descrip tion........................................................................................................ .11 6.1 power on st rapping................................................................................................... 11 6.2 keyboard c ontroller .................................................................................................. 11 6.3 acpi f unction ............................................................................................................ 13 6.4 hardware monitor ...................................................................................................... 18 6.5 led f unction ............................................................................................................. 27 6.6 amd tsi and intel sst peci func tion ..................................................................... 27 6.7 watchdog timer function ......................................................................................... 28 7. register descrip tion ........................................................................................................ .29 7.1 global control register s ........................................................................................... 29 7.2 kbc regi sters........................................................................................................... 32 7.3 acpi and pme registers.......................................................................................... 34 7.4 hardware monitor registers (ind ex port: 0x295; data port: 0x296) .......................... 38 7.5 gpio regi sters ......................................................................................................... 60 7.6 wdt regi sters.......................................................................................................... 65 8. pcb layout guide ........................................................................................................... 6 7 9. electrical c haracteri stics .................................................................................................. 69 9.1 absolute maxi mum rati ngs ...................................................................................... 69 9.2 dc characte ristics .................................................................................................... 69 9.3 dc characterist ics conti nued ................................................................................... 69 9.4 ac characte ristics .................................................................................................... 71 10. ordering informa tion ....................................................................................................... .75 11. package dimensions (48lqfp )....................................................................................... 76 12. applicat ion cir cuit........................................................................................................ ..... 77
aug, 2010 v0.12p 4 F71858AD 1. general description the F71858AD is hardware kbc integrating the acpi, temperature sensing and fan control functions specific for the legacy free mb application. the kbc functions include one keyboard and one ps/2 mouse, and can be used with ibm ? - compatible personal computers or ps/2-based systems. the controller receives serial data from the keyboard or ps/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. the controller will assert an interrupt to the system when data are placed in its output buffer. the F71858AD provides the acpi control signals as well such as s3 state, resume reset, 12 pins gpio, wdt, pci reset outputs or power ok signals. the power led is programmable and compliant with pc2001. as to the environment sensing functions, F71858AD provides 2 remote analog dual current temp. sensing inputs and one internal local temperature sensing. one hw_irq (alert signal) will be issued while the temperature is over the pr ogrammable limit. 4 fan monitoring inputs and 3 fan controlling outputs provide fintek?s patented auto-fan controlling features. besides, the F71858AD supports amd tsi and intel peci/sst interfaces for next generation cpu temp. sensing technology. F71858AD is in lpc interface and powered by 3vcc, 3v standby, and battery. the package is in 48 pin lqfp green package. 2. feature list general functions ? comply with lpc spec. 1.1 ? hardware keyboard controller support one ps/2 keyboard and one ps/2 mouse ? hardware gate a20 and hardware keyboard reset ? support acpi 3.0 ? 12 gpio pins ? wdt signal ? hwm functions (also support peci fan control mechanism) kbc ? lpc interface support serial interrupt channel 1, 12. ? two 16bit programmable address fully decoder, default 0x60 and 0x64. ? support two ps/2 interface, one for ps/2 mouse and the other for keyboard.
aug, 2010 v0.12p 5 F71858AD ? keyboard?s scan code support set1, set2. ? programmable compatibility with the 8042. ? support both interrupt and polling modes. ? hardware gate a20 and hardware keyboard reset. acpi functions ? 1 reset input and 5 pci reset output pins ? 2 programmable power led ? s3gate control ? resume reset ? power ok signal hardware monitor functions ? 2 current type accurate (3 ) thermal inputs for cpu thermal diode/2n3906 transistors ? one internal local thermal sensor ? pin hw_irq# (default limit 100c for cpu temp.) ? temperature sensing range from -40 ~127 ? 4 fan speed monitoring inputs ? 3 fan speed auto-control (support 3 wire and 4 wire fans) ? support pwm and dac mode control ? default pwm duty is 40% when system boot up promptly ? provide intel peci/sst interface for temperature sensing ? provide amd tsi interface for temperature sensing ? support 3 channels voltage monitor ( vcc3v + vsb3v + vbat) ? voltage monitor resolution is 8mv per lsb gpio function ? total 12 pins gpio ? gpio supports interrupt event by pme/serirq watch dog timer ? time resolution minute/second by option ? maximum 256 minutes or 256 seconds ? output wdt signal via pwok pin package ? 48-pin lqfp
aug, 2010 v0.12p 6 F71858AD 3. key specification supply voltage 3.0v to 3.6v operating supply current 5 ma typ.
aug, 2010 v0.12p 7 F71858AD 4. pin configuration
aug, 2010 v0.12p 8 F71858AD 5. pin description i/o 12t - ttl level bi-directional pin with 12 ma source-sink capability. i/ood 12st,5v i/ood 16st,5v - ttl level bi-directional pin and schmitt trigger, can select to od or out by register, with 12 ma so urce-sink capability. - ttl level bi-directional pin and schmitt trigger, can select to od or out by register, with 16 ma source-sin k capability, 5v tolerance. od 16u,10k od 16,5v i/od 12st,5v i/od 12t,5v - open-drain output pin with 16 ma sink capability, pull-up 10k ohms. - open-drain output pin with 16 ma sink capability, 5v tolerance. - ttl level bi-directional pin and schmitt trigger, open-drain output with 12 ma sink capability, 5v tolerance. -ttl level bi-directional pin, open-drain output with 12 ma sink capability, 5v tolerance. o 16 -output pin with 16 ma source-sink capability. od 12 od 12,5v in t,5v - open-drain output pin with 12 ma sink capability - open-drain output pin with 12 ma sink capability, 5v tolerance. - ttl level input pin,5v tolerance. in t,5v in st - ttl level input pin,5v tolerance. - ttl level input pin and schmitt trigger. in t - ttl level input pin in st,5v - ttl level input pin and schmitt trigger, 5v tolerance. i lv /o d8,s1 - bi-directional pin with 8ma source and 1ma sink capability, input level over 0.9v for high and under 0.5v for low . i lv /od 12 - bi-directional pin with 12ma sink capability, input level over 0.9v for high and under 0.5v for low . i lv /ood 12 - bi-directional pin, can select to od or out by register, with 12ma source-sink capability, input level over 0.9v for high and under 0.5v for low . in lv - input pin, input level over 0. 9v for high and under 0.5v for low . aout - output pin(analog). ain - input pin(analog). p - power. 5.1 power pin pin no. pin name type description 9 vcc p 3v power 21 gnd(d-) p ground for te mperature sensing usage. 24 avcc3v p 3v power for analog (provide voltage monitor) 40 vsb3v p 3v stand by power (provide voltage monitor) 45 gnd p ground 48 vbat p battery power (provide voltage monitor) 5.2 lpc interface pin no. pin name type pwr description 1 lreset# in st,5v vcc reset signal. it can connect to pcirst# signal on the host. 2 lframe# in st vcc indicates start of a new cycle or termination of a
aug, 2010 v0.12p 9 F71858AD broken cycle. 3,4,5,6 lad[3:0] i/o 12t vcc these signal lines communicate address, control, and data information over the lpc bus between a host and a peripheral. 7 pciclk in t vcc 33mhz pci clock input. 8 serirq i/o 12t vcc serial irq input/output. 5.3 keyboard controller pin no. pin name type pwr description 18 ga20 od 16,u10k vcc gate a20 output. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p21) 19 kbrst# od 16-u10k vcc keyboard reset. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p20) kclk i/od 16st,5v vsb keyboard clock. 41 gpio10 i/ood 16st,5v vsb general purpose io kdata i/od 16st,5v vsb keyboard data. 42 gpio11 i/ood 16st,5v vsb general purpose io mclk i/od 16st,5v vsb ps2 mouse clock. 43 gpio12 i/ood 16st,5v vsb general purpose io mdata i/od 16st,5v vsb ps2 mouse data. 44 gpio13 i/ood 16st,5v vsb general purpose io 5.4 acpi pin no. pin name type pwr description rstin# in st,5v vsb reset buffer input signal. 25 gpio03 i/ood 12st,5v vsb general purpose io 26 pcirst1# od 16,5v vsb output buffer of rstin# and lreset# for ide reset. 27,28 pcirst[2:3]# o 16 vsb output buffer of rstin# and lreset#. pcirst4# o 16 vsb output buffer of rstin# and lreset#. 29 gpio04 i/ood 16st,5v vsb general purpose io pcirst5# od 16,5v vsb output buffer of rstin# and lreset# for ide reset. 30 gpio05 i/ood 16st,5v vsb general purpose io led1 od 16,5v vsb power led for vsb. 31 gpio06 i/ood 16st,5v vsb general purpose io led2 od 16,5v vsb power led for vsb. 32 gpio07 i/ood 16st,5v vsb general purpose io 33 s3gate od 12,5v vsb control dual voltage signal. 34 ps_on# od 12,5v vsb power supply on-off control output. connect to atx power supply ps_on# signal. 35 s3# in st vsb s3# input is main power on-off switch input. 36 s4# in st vsb s4# input is for s3/s4 (s5) state switch input. 38 ps_out# od 12 vsb panel switch output. this pin is low active and pulse output. it is power on request output#.
aug, 2010 v0.12p 10 F71858AD 39 ps_in# in st,5v vsb main power switch button input. 46 pwok i/od 12t,5v vbat pwok function, it is power good signal of vcc, which is delayed 400ms (default and programmable) as vcc arrives at 2.8v. watchdog signal can be asserted via this pin. 47 rsmrst# od 12 vbat resume reset# function, it is power good signal of vsb, which is delayed 66ms as vsb arrives at 2.3v. 5.5 h/w monitor pin no. pin name type pwr description peci i lv /o d8,s1 intel peci hardware monitor interface. amdtsi_data i lv /od 12 amd tsi data interface. 10 gpio00 i lv /ood 12 vcc general purpose io 11 fan_ctl1 od 12, 5v aout vcc fan 1 control output. this pin provides pwm duty-cycle output or a voltage output. default pwm duty is 40%. 12 fan_ctl2 od 12,5v aout vcc fan 2 control output. this pin provides pwm duty-cycle output or a voltage output. default pwm duty is 40%. fan_ctl3 od 12,5v aout vcc fan 3 control output and 3pin fan is recommended to be controlled by this pin but not 4pin fan. this pin provides pwm duty-cycle output or a voltage output. 13 pwm_dc in t,5v vcc power on strapping : pull high: fan control method will be in pwm mode nc: fan control method will be in dac mode 14 fanin1 in st,5v vcc fan 1 tachometer input. 15 fanin2 in st,5v vcc fan 2 tachometer input. fanin3 in st,5v vcc fan 3 speed input. default pwm duty is 40%. 16 gpio01 i/ood 12st,5v vcc general purpose io fanin4 in lv fan 4 speed input. sst i lv /o d8,s1 intel sst hardware monitor interface. amdtsi_clk od 12 clock output for amd tsi interface. 17 gpio02 i lv /ood 12 vcc general purpose io 20 hw_irq# od 12,5v vcc active low output. this pin will be logic low when the temperature exceeds its limit or fan fault event. 22 d1+(cpu) aout ain vcc thermal diode/transistor temperature sensor input. 23 d2+ aout ain vcc thermal diode/transistor temperature sensor input. 37 pme# od 12 vsb generated pme event. it supports the pci pme# interface. this signal allows the peripheral to request the system to wake up from the s3 state.
aug, 2010 v0.12p 11 F71858AD 6. function description 6.1 power on strapping pin no. symbol value description 1 fan control mode: pwm mode. ( default) 13 pwm_dc 0 fan control mode: dac mode. 6.2 keyboard controller the kbc circuit provides the functions included a keyboard and/or a ps/2 mouse, and can be used with ibm ? - compatible personal computers or ps/2-based systems. the controller receives serial data from the keyboard or ps/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. the controller will assert an interrupt to the system when data are placed in its output buffer. output buffer the output buffer is an 8-bit read-only register at i/o address 60h. the keyboard controller uses the output buffer to send the scan code rece ived from the keyboard and data bytes required by commands to the system. input buffer the input buffer is an 8-bit write-only register at i/o address 60h or 64h. writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. data written to i/o address 60h is sent to keyboard through the controller's input buffer only if the input buffer full bit in the status register is ?0?. status register the status register is an 8-bit read-only register at i/o address 64h that holds information about the status of the keyboard controller and interface. it may be read at any time. bit bit function description 0 output buffer full 0: output buffer empty 1: output buffer full 1 input buffer full 0: input buffer empty 1: input buffer full
aug, 2010 v0.12p 12 F71858AD 2 system flag this bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller (kccb). it defaults to 0 after a power-on reset. 3 command/data 0: data byte 1: command byte 4 inhibit switch 0: keyboard is inhibited 1: keyboard is not inhibited 5 mouse output buffer 0: muse output buffer empty 1: mouse output buffer full 6 general purpose time-out 0: no time-out error 1: time-out error 7 parity error 0: odd parity 1: even parity (error) commands command function 20h read command byte 60h write command byte bit description 0 enable keyboard interrupt 1 enable mouse interrupt 2 system flag 3 reserve 4 disable keyboard interface 5 disable mouse interface 6 ibm keyboard translate mode 7 reserve a7h disable auxiliary device interface a8h enable auxiliary device interface a9h auxiliary interface test 8?h00: indicate auxiliary interface is ok. 8?h01: indicate auxiliary clock is low. 8?h02: indicate auxiliary clock is high 8?h03: indicate auxiliary data is low 8?h04: indicate auxiliary data is high aah self-test returns 055h if self test succeeds
aug, 2010 v0.12p 13 F71858AD abh keyboard interface test 8?h00: indicate keyboard interface is ok. 8?h01: indicate keyboard clock is low. 8?h02: indicate keyboard clock is high 8?h03: indicate keyboard data is low 8?h04: indicate keyboard data is high adh disable keyboard interface aeh enable keyboard interface c0h read input port(p1) and send data to the system c1h continuously puts the lower four bi ts of port1 into status register c2h continuously puts the upper four bi ts of port1 into status register d0h send port2 value to the system d1h only set/reset gatea20 line based on the system data bit 1 d2h send data back to the system as if it came from keyboard d3h send data back to the system as if it came from muse d4h output next received byte of data from system to mouse feh pulse only rc (the reset line) low for 6 s if command byte is even kbc command description ps2 wakeup function the kbc supports keyboard and mouse wakeup function. when pressing combinational keys as (1) ctrl +esc (2) ctrl+f1 (3) ct rl+space (4) any key (5) windows 98 wakeup up key under keyboard wakeup function, kbc will assert pme signal. kbc will also assert pme signal via mouse?s (1) button click or (2) bu tton click and movement. those wakeup conditions are controlled by configuration register. 6.3 acpi function the advanced configuration and power interface (acpi) is a system for controlling the use of power in a computer. it lets computer manufacturer and user to determine the computer?s power usage dynamically. there are three acpi states that are of primar y concern to the system designer and they are designated s0, s3 and s5. s0 is a full-power state; the computer is being actively used in this state. the other two are called sleep states and reflect different power consumption when power-down. s3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. s5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. take s3 and s5 as comparison, since memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer
aug, 2010 v0.12p 14 F71858AD takes longer time to come back to full-power state. however, since the memory is off, s5 draws the minimal power comparing to s0 and s3. it is anticipated that only the following state transitions may happen: s0 s3, s0 s5, s5 s0, s3 s0 and s3 s5. among them, s3 s5 is illegal transition and won?t be allowed by state machine. it is necessary to enter s0 first in order to get to s5 from s3. as for transition s5 s3 will occur only as an immediate state during state transition from s5 s0. it isn?t allowed in the normal state transition. the below diagram described the timing, the always on and always off, keep last state could be set in control register. in keep last state mode, one register will keep the status of before power loss. if it is power on before power loss, it will remain power on when power is resumed, otherwise, if it is power off before power loss, it will remain power off when power is resumed. vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v acpi default timing always off
aug, 2010 v0.12p 15 F71858AD rsmrst# ps_on# psin# psout# vcc3v vbat vsb s3# acpi default timing always on
aug, 2010 v0.12p 16 F71858AD pcirst and pwrok signals the F71858AD supports 5 output buffers for 5 reset signals. the result of pcirst [1:5]# outcome will be affected by conditions as below. the pwrok signal is affected by rst_in#/lreset#/dvcc3vok.when rstcon_en set 1, powerok signal is affected by d_vcc3vok and when rstcon_en set 0, powerok signal is affected by rst_in#/ lreset#/d_vcc3vok.see below for the reference. pcirst# and pwrok rstcon_en 50ms rstin# lreset# rst_da rst_dis pcirst rstcon_en 1 0 0 1 rstin# 50ms d_vcc3vok d_vcc3v o k pwok 1ms
aug, 2010 v0.12p 17 F71858AD s4# s3gate s3# s5 state s0 state s5 state ~10us ~400ms vddok s3 state s0 state ~400ms s3 gate signals the s3gate signal response s0/s3/s5 state and condition is as below. when system is in s3 state, s3gate is asserted logic high; the other state is asserted logic low. it is anticipated that only the following state transitions may happen: s0 s3, s0 s5, s5 s0, s3 s0 and s3 s5. among them, s5 s3 is illegal transition and s3gate signal will be keep logic level. s3gate timming
aug, 2010 v0.12p 18 F71858AD 6.4 hardware monitor for the 8-bit adc has the 8mv lsb, the maximum input voltage of the analog pin is 2.04v. therefore the voltage under 2.04v (ex:1.5v) can be directly connected to these analog inputs. the voltage higher than 2.04v should be reduced by a factor with external resistors so as to obtain the input range. vcc, vsb 3.3v and vbat 3v are the exception for it is main power of the F71858AD. therefore these powers can directly connect to this chip?s power pin and need no external resistors. there are two functions in these pins with 3.3v/3v. the first function is to supply internal logic power of the F71858AD and the second function is that this voltage with 3.3v/3v is connected to internal serial resistors to monitor the vcc vsb 3.3v and vbat voltage. the internal serial resistors are two 150k ohm, so that the internal reduced voltage is half of 3.3v/3v. F71858AD only support three power voltage monitor but without hardware high low limit protect. so it will not trigger pme event when voltage too high or too low. 8-bit adc with 8 mv lsb voltage inputs (directly connect to the chip) 3vcc (directly connect to the chip) vin1 150k 150k 2n3906 typical bjt connection d+ gnd 3vsb 3vbat the F71858AD monitors a local and 2 remote temperature sensor. both can be measured from -40c to 127c. the temperature format is as the following table: table mode: display range is from -40c to 127c. the values in high byte registers bit7 is sign bit and the values in high byte registers bit6~bit0 are mean temperature reading value and the unit is 1c. the value in low bye register bit7~bit5 are temperature reading value and the unit is 0.125c. temperature digital output (high byte) digital output (low byte) -40c 1101 1000 000x xxxx -1c 1111 1111 000x xxxx 0c 0000 0000 000x xxxx
aug, 2010 v0.12p 19 F71858AD 100c 0110 0100 000x xxxx 127.875c 0111 1111 111x xxxx open 1011 1011 000x xxxx short 1100 1100 000x xxxx remote-sensor transistor manufacturers manufacturer model number panasonic 2sb0709 2n3906 philips pmbt3906 monitor temperature from ?thermal diode? also, if the cpu, gpu or external circuits provide thermal diode for temperature measurement, the F71858AD is capable to these situations. the build-in reference table is for pnp 2n3906 transistor, and each different kind of thermal diode should be matched with specific margin and bjt gain. the transistor is directly connected into temperature pins. adc noise filtering the adc is integrating type with inherently good noise rejection. micro-power operation places constraints on high-frequency noise rejection; therefore, careful pcb board layout and suitable external filtering are required for high-accuracy remote measurement in electronically noisy environment. high frequency emi is best filtered at d+ and d- with an external 2200pf or 3300pf capacitor. too high capacitance may introduce errors due to the rise time of the switched current source. nearly all noise sour ces tested cause the adc measurement to be higher than the actual temperature, depending on the frequency and amplitude. temperature hm_irq signal (hm_irq# and pme#) there are two mode of temperature hm_irq function: 1. hysteresis mode: over temperature event will trigger hm_irq# that shown as figure. in hysteresis mode, when monitored temperature exceeds the high te mperature threshold value, hm_irq# will be asserted until the temperature goes below the hysteresis temperature.
aug, 2010 v0.12p 20 F71858AD t hyst t hm_irq# high 2. high low limit mode: (default): when in high low limit mode hm_irq# for temperature is shown as figure. when monitored temperature exceeds the over-tem perature threshold value, hm_irq# will be asserted until the temperature goes below the low limit temperature. t low hm_irq# t high temperature pme# there are two mode of temperature pme# function: 1. hysteresis mode: pme# interrupt for temperature is shown as figure. temperature exceeding high limit (low limit) or going below high hysteresis (low hy steresis) will cause an interrupt if the previous interrupt has been reset by writing ?1? all the interrupt status register.
aug, 2010 v0.12p 21 F71858AD *interrupt reset when interrupt status registers are written 1 pme# t low (pulse mode) * * t high t hhys t lhys * * 2. high low limit mode: (default): pme# interrupt for temperature is shown as figure. temperature exceeding high limit or going below low limit will cause an interrupt if the previous interrupt has been reset by writing ?1? all the interrupt status register. *interrupt reset when interrupt status registers are written 1 pme# t low (pulse mode) * t high * fan speed count inputs are provided by the signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage cannot be over 5v. if the input signals from the tachometer outputs are over the 5v, the external trimming circuit should be added to reduce the voltage to obtain the input specification.
aug, 2010 v0.12p 22 F71858AD fanin monitor dc output voltage +12v r10k 1 2 3 jp1 con3 r 10k r 3.6k d1 1n4148 3 2 1 8 4 + - u1a lm358 r27k r 4.7k c 47u q1 pmos c 0.1u r 4.7k determine the fan counter according to the following equation: rpm 10 5 . 1 count 6 = in other words, the fan speed counter has been read from register, the fan speed can be evaluated by the following equation. as for fan, it would be best to use 2 pulses tachometer output per round. count 10 5 . 1 rpm 6 = fan speed control the F71858AD provides 2 fan speed control methods: 1. dac fan control 2. pwm duty cycle dac fan control the range of dc output is 0~ vcc , controlled by 8-bit register. 1 lsb is about 0.013v (vcc=3.3v) . the output dc voltage is amplified by external op circuit, thus to reach maximum fan operation voltage, 12v. the output voltage will be given as followed: 256 value register 8bit programmed vcc (v) tage output_vol = and the suggested application circuit for dac fan control would be: pwm duty fan control the duty cycle of pwm can be programmed by a 8-bit register. the default duty cycle is set to 40%, that is, the default 8-bit registers is set to 66h. the expression of duty can be represented as follows. % 100 255 value register 8bit programmed (%) duty_cycle =
aug, 2010 v0.12p 23 F71858AD +12v fan r1 r2 nmos pnp transisto r c + - d s g fan speed control mechanism there are some modes to control fan speed and they are 1.manual mode, 2.stage auto mode, 3.linear auto mode. more detail, please refer the description of registers. manual mode: for manual mode, it generally acts as software fan speed control. stage auto mode: at this mode, the F71858AD provides automatic fan speed control related to positive or negative temperature variation of cpu/gpu or the system. the F71858AD can provide four temperature boundaries and five intervals, and each interval has its related fan speed count. all these values should be set by bios first. take below figure as an example. when temperature boundaries are set as 40, 50, 60, and 70 c (each interval differs10 c), the related desired pwm duty for each interval is 100%, 85%, 65%, 50%, and 40%. when the temperature is within 50~60 c, the duty is 65%. then, the F71858AD will adjust pwmout duty-cycle to meet the expected value. it can be said that the fan will be turned on with a specific speed set by bios and automatically controlled with the temperature variation. the F71858AD will take charge of all the fan speed control and does not require any software support. desired duty (default 100%) (default 85%) (default 65%) (default 50%) (default 40%) boundtemp1 (default 70'c) boundtemp2 (default 60'c) boundtemp3 (default 50'c) boundtemp4 (default 40'c) there are two examples as below:
aug, 2010 v0.12p 24 F71858AD a. stage auto mode (pwm duty) set temperature as 60 c, 50 c, 40 c, 30 c and duty as 100%, 90%, 80%, 70%, 60% 100% 90% 80% 70% 60% 60 degree c 50 degree c 40 degree c 30 degree c 0xff 0xe5 0xcc 0xb2 0x99 ab cd temp. fan speed pwm duty hysteresis 47 degree c a. once temp. is under 30 c, the lowest fan speed keeps 60% pwm duty b. once temp. is over 30 c,40 c,50 c, the fan speed will vary from 60% to 90% pwm duty and increase with temp. level. c. once temp. keeps in 55 c, fan speed keeps in 90% pwm duty d. if set the hysteresis as 3 c (default 4 c), once temp reduces under 47 c, fan speed reduces to 80% pwm duty and stays there. b. stage auto mode (rpm%) set temperature as 60 c, 50 c, 40 c, 30 c and assume the full speed is 6000rpm, set 90% of full speed rpm(5400rpm), 80%(4800rpm ), 70%(4200rpm), 60%(3600rpm) of full speed rpm 6000rpm 90%(5400rpm) 80%(4800rpm) 70%(4200rpm) 60%(3600rpm) 60 degree c 50 degree c 40 degree c 30 degree c ab cd tem p . fan s p eed hysteresis 47 degree c a. once temp. is under 30 c, the lowest fan speed keeps 60% of full speed (3600rpm). b. once temp. is over 30 c,40 c,50 c, the fan speed will vary from 3600rpm to 5400rpm and increase with temp. level. c. once temp. keeps in 55 c, fan speed keeps in 90% of full speed (5400rpm) d. if set the hysteresis as 3 c (default 4 c), once temp reduces under 47 c, fan speed
aug, 2010 v0.12p 25 F71858AD reduces to 4800rpm and stays there. linear auto mode: otherwise, F71858AD supports linear auto mode. be low two examples are to describe this mode. more detail, please refer the register description. a. linear auto mode (pwm duty) set temperature as 70 c, 60 c, 50 c, 40 c and duty as 100%, 70%, 60%, 50%, 40% 100% 70% 60% 50% 40% 70 degree c 60 degree c 50 degree c 40 degree c ab c d hysteresis 65 degree c temp. fan speed pwm duty a. once temp. is under 40 c, the lowest fan speed keeps 40% pwm duty b. once temp. is over 40 c,50 c,60 c, the fan speed will vary from 40% to 70% pwm duty and linearly increase with temp. variation. the temp.-fan speed monitoring and flash interval is 1sec. c. once temp. goes over 70 c, fan speed will directly increase to 100% pwm duty (full speed) d. if set the hysteresis as 5 c(default is 4 c), once temp reduces under 65 c (not 70 c), fan speed reduces from 100% pwm duty and decrease linearly with temp.. b. linear auto mode (rpm%) set temperature as 70 c, 60 c, 50 c, 40 c and if full speed is 6000rpm, setting 100%, 70%, 60%, 50%, 40% of full speed. 6000rpm 70%(4200rpm) 60%(3600r pm) 50%(3000r pm) 40%(2400rp m) 70 degree c 60 degree c 50 degree c 40 degree c ab c d hysteresis 65 degree c temp. fan speed a. once temp. is under 40 c, the lowest fan speed keeps 40% of full speed (2400rpm) b. once temp. is over 40 c,50 c,60 c, the fan speed will vary from 40% to 70% of full
aug, 2010 v0.12p 26 F71858AD speed and almost linearly increase with temp. variation. the temp.-fan speed monitoring and flash interval is 1sec. c. once temp. goes over 70 c, fan speed will directly increase to full speed 6000rpm. d. if set the hysteresis as 5 c, once temp reduces under 65 c (not 70 c), fan speed reduces from full speed and decrease linearly with temp.. pwmout duty-cycle operating process in both ?manual rpm? and ?temperature rpm? modes, the F71858AD adjust pwmout duty-cycle according to current fan count and ex pected fan count. it will operate as follows: (1). when expected count is 0xfff, pwmout duty-cycle will be set to 0x00 to turn off fan. (2). when expected count is 0x000, pwmout duty-cycle will be set to 0xff to turn on fan with full speed. (3). if both (1) and (2) are not true, when pwmout duty-cycle decrease to min_duty( 00h), obviously the duty-cycle will decrease to 00h next, when F71858AD up the fan speed will keep duty-cycle at start duty for 1.2 seconds. after that, the F71858AD starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. this ensures that if there is any glitch during the period, the F71858AD will ignore it. start duty stop duty fan hm_irq signal (hm_irq# and pme#) fan fault will be asserted when the fan speed doesn?t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to pwm duty-cycle which should be able to turn on the fan. there are two conditions may cause the fan_fault# event. (1). when pwm_duty reaches 0xff, the fan speed count can?t reach the fan expected count in time.
aug, 2010 v0.12p 27 F71858AD fan_fault# expected fan count 11 sec ( default ) current fan count duty-cycle 100% (2). after the period of detecting fan full speed, when pwm_duty > min. duty, and fan count still in 0xfff. 6.5 led function the F71858AD provides two leds to indicate system state (s0, s3, and s5) which could be controlled via configuration register. system state could be set as (1) always 0 (2) oscillate 1hz (3) oscillate 1/2 hz and (4) always 1. when system is in s0, led1 is default as 0 and led2 as 1. when system is in s3, led1 and led2 oscillate 1hz. when system is in s5, led1 is default as 1 and led2 as 0. 6.6 amd tsi and intel sst peci function the F71858AD provides intel sst/peci/amd tsi interfaces for new generational cpu temperature sensing. there are scl and sda signals for temperature reading from amd cpu via tsi interface. the scl signal is for clocking usage, and other is for data transferring. more detail please refer to the register description. vddi sic sid 300 F71858AD amd cpu sic sid 300 in intel sst and peci interfaces, the F71858AD can connect to cpu/sst directly. the F71858AD can read the temperature data from cpu, than the fan control machine of F71858AD can implement the fan to cool down cpu temperature. as same as peci, chipset can get information
aug, 2010 v0.12p 28 F71858AD from F71858AD including cpu temperature, syst em temperature (F71858AD provides d+/d- for system temperature sensing), fan speed status by sst. the application circuit is as below. more detail please refer to the register description. sst F71858AD ich8 sst intel peci F71858AD cpu peci intel 100 6.7 watchdog timer function watch dog timer is provided for system contro lling. if time-out can trigger one signal to high/low level/pulse, the signal is depended on register setting. the time unit has two ways from 1sec or 60sec. in pulse mode, there are four pulse widths can be selected (1ms/25ms/125ms/5sec). please refer to the device register description for detail.
aug, 2010 v0.12p 29 F71858AD 7. register description 7.1 global control registers the configuration register is used to control the behavior of the corresponding devices. to configure the register, using the index port to select the index and then writing data port to alter the parameters. the default index port and data port are 0x4e and 0x4f respectively. to enable configuration, the entry key 0x87 must be written to the index port. to disable configuration, write exit key 0x78 twice or key 0xaa once to the index port. following is an example to enable configuration and disable configuration by using debug. -o 4e 87 -o 4e 87 ( enable configuration ) -o 4e aa ( disable configuration ) 7.1.1 software reset register ? index 02h bit name r/w default description 7-1 reserved - - reserved 0 soft_rst r/w 0 write 1 to reset the r egister and device powered by vdd (vcc). 7.1.2 logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select kbc device c onfiguration registers. 01h: select pme & acpi device configuration registers. 02h: select hardware monitor dev ice configuration registers. 03h: select gpio device c onfiguration registers. 04h: select wdt device configuration registers. 7.1.3 chip id register ? index 20h bit name r/w default description 7-0 chip_id1 r 09h chip id 1 of F71858AD. 7.1.4 chip id register ? index 21h bit name r/w default description 7-0 chip_id2 r 03h chip id2 of F71858AD.
aug, 2010 v0.12p 30 F71858AD 7.1.5 vendor id register ? index 23h bit name r/w default description 7-0 vendor_id1 r 19h vendor id 1 of fintek devices. 7.1.6 vendor id register ? index 24h bit name r/w default description 7-0 vendor_id2 r 34h vendor id 2 of fintek devices. 7.1.7 port select register ? index 25h bit name r/w default description 7-5 reserved - - reserved. 4 port_4e_en r/w 1 the port could be changed by writing this register. 0: configuration register port is 2e/2f. 1: configuration register port is 4e/4f. (default) 3-0 reserved - - reserved. 7.1.8 select kb/mo wake up register ? index 27h (powered by vbat) bit name r/w default description 7 dis_wakeup r/w 0 0: enable kb/mo wakeup function. 1: disable kb/mo wakeup function 6 vsbok_hys_dis r/w 0 0: enable vsbok detect hysteresis. 1: disable vsbok detect hysteresys. 5 vsbok_lvl_sel r/w 0 0: vsb3v power good level is 2.8v and not good level is 2.5v. 1: vsb3v power good level is 3.05v and not good level is 2.95v. by vsbok_hys_dis and vsbok_lvl_sel, rsmrst# falling edge could be determined: 00: when vsb3v is lower than 2.5v. 01: when vsb3v is lower than 2.95v. 10: when vsb3v is lower than 2.8v. 11: when vsb3v is lower than 3.05v. 4 reserved - 0 reserved. 3 key_sel_add r/w 0 this bit is added to add more wakeup key function. 2 mo_sel r/w 0 select mouse key to wakeup host 0: click mouse key 1:any mouse key
aug, 2010 v0.12p 31 F71858AD 1-0 key_sel r/w 00 this registers select the keyboard wake up key. accompanying with key_sel_add, there are eight wakeup keys: key_sel_add key_sel wakeup key 0 00 ctrl + esc 0 01 ctrl + f1 0 10 ctrl + user_wakeup_code (space) 0 11 any key 1 00 windows wakeup 1 01 windows power 1 10 ctrl + alt + user_wakeup_code (space) 1 11 user_wakeup_code (space) 7.1.9 multi-function select register 1 ? index 28h (powered by vsb3v) bit name r/w default description 7 reserved - - reserved. 6 gpio03_en r/w 0 rstin#/gpio03 function select. 0: pin function is rstin#. 1: pin function is gpio03. 5-4 gpio02_sel r/w 0 fanin4/sst/amdtsi_clk/gpio02 function select. 00: pin function is fanin4. 01: pin function is sst. 10: pin function is amdtsi_clk. 11: pin function is gpio02. 3 reserved - - reserved. 2 gpio01_en r/w 0 fanin3/gpio01 function select. 0: pin function is fanin3. 1: pin function is gpio01. 1-0 gpio00_sel r/w 0 peci/amdtsi_dat/gpio00 function select. 00: pin function is peci. 01: reserved. 10: pin function is amdtsi_dat. 11: pin function is gpio00.
aug, 2010 v0.12p 32 F71858AD 7.1.10 multi-function select register 2 ? index 29h (powered by vsb3v) bit name r/w default description 7 gpio07_en r/w 0 led2/gpio07 function select. 0: pin function is led2. 1: pin function is gpio07. 6 gpio06_en r/w 0 led1/gpio06 function select. 0: pin function is led1. 1: pin function is gpio06. 5 gpio05_en r/w 0 pcirst5#/gpio05 function select. 0: pin function is pcirst5#. 1: pin function is gpio05. 4 gpio04_en r/w 0 pcirst4#/gpio04 function select. 0: pin function is pcirst4#. 1: pin function is gpio04. 3-2 reserved - - reserved. 1 kb_gp_en r/w 0 keyboard interface and gpio function select. 0: pin 41 and 42 are kclk and kdata respectively. 1: pin 41 and 42 are gpio10 and gpio11 respectively. 0 mo_gp_en r/w 0 mouse interface and gpio function select. 0: pin 43 and 44 are mclk and mdata respectively. 1: pin 43 and 44 are gpio12 and gpio13 respectively. 7.2 kbc registers 7.2.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select kbc device c onfiguration registers. 01h: select pme & acpi device configuration registers. 02h: select hardware monitor dev ice configuration registers. 03h: select gpio device c onfiguration registers. 04h: select wdt device configuration registers. 7.2.2 kbc configur ation registers kbc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 kbc_en r/w 1 0: disable kbc. 1: enable kbc.
aug, 2010 v0.12p 33 F71858AD base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of kbc base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 60h the lsb of kbc base address. keyboard irq channe l enable register ? index 70h bit name r/w default description 7-6 reserved - - reserved. 0 enkbcirq r/w 1 enable the irq channel for keyboard. mouse irq channel enable register ? index 72h bit name r/w default description 7-6 reserved - - reserved. 0 enmocirq r/w 1 enable the irq channel for mouse. auto swap register ? index feh (powered by vbat) bit name r/w default description 7 auto_det_en r/w 0 0: disable auto detect keyboard/mouse swap. 1: enable auto detect keyboard/mouse swap. 6-5 reserved - - reserved. 4 kb_mo_swap r/w 0 0: keyboard/mouse does not swap. 1: keyboard/mouse swap. this bit is set/clear by hardware if auto_det_en is set to ?1?. users could also program this bit manually. 3-0 reserved - - reserved user wakeup code register ? index ffh (powered by vbat) bit name r/w default description 7-0 user_wakeup_co de r/w 29h this is user define wakeup code. default is space.
aug, 2010 v0.12p 34 F71858AD 7.3 acpi and pme registers 7.3.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select kbc device c onfiguration registers. 01h: select pme & acpi device configuration registers. 02h: select hardware monitor dev ice configuration registers. 03h: select gpio device c onfiguration registers. 04h: select wdt device configuration registers. 7.3.2 acpi and pme conf iguration registers device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 pme_en r/w 0 0: disable pme. 1: enable pme. pme event enable register ? index f0h bit name r/w default description 7 wdt_pme_en r/w 0 watchdog timer pme event enable. 0: disable watchdog timer pme event. 1: enable watchdog timer pme event. 6 ms_pme_en r/w 0 ps/2 mouse pme event enable. 0: disable ps/2 mouse pme event. 1: enable ps/2 mouse pme event. 5 kb_pme_en r/w 0 ps/2 keyboard pme event enable. 0: disable ps/2 keyboard pme event. 1: enable ps/2 keyboard pme event. 4 gp_pme_en r/w 0 gpio pme event enable. 0: disable gpio pme event. 1: enable gpio pme event. 3-1 reserved - - reserved 0 hm_pme_en r/w 0 hardware monitor pme event enable. 0: disable hardware monitor pme event. 1: enable hardware monitor pme event. pme event status register ? index f1h bit name r/w default description 7 wdt_pme_st r/wc - watchdog timer pme event status. 0: watchdog timer has no pme event. 1: watchdog timer has a pme event to assert. write 1 to clear to be ready for next pme event.
aug, 2010 v0.12p 35 F71858AD 6 ms_pme_st r/w 0 ps/2 mouse pme event status. 0: ps/2 mouse has no pme event. 1: ps/2 mouse has a pme event to asser t. write 1 to clear to be ready for next pme event. 5 kb_pme_st r/w 0 ps/2 keyboard pme event status. 0: ps/2 keyboard has no pme event. 1: ps/2 keyboard has a pme event to assert. write 1 to clear to be ready for next pme event. 4 gp_pme_st r/wc - gpio pme event status. 0: gpio has no pme event. 1: gpio has a pme event to assert. write 1 to clear to be ready for next pme event. 3-1 reserved - - reserved 0 hm_pme_st r/w 0 hardware monitor pme event status. 0: hardware monitor has no pme event. 1: hardware monitor has a pme event to assert. write 1 to clear to be ready for next pme event. acpi control register ? index f4h bit name r/w default description 7 ts3 r/w 0 set to 1 to enable keyboard or mouse can wakeup from s1 state, it must also set en_kbcwakeup and en_mowakeup register. 6-5 reserved - - reserved. 4 enkbwakeup r/w 0 0:disable keyboard wakeup signal (ps_out#) 1:enable keyboard wakeup signal 3 enmowakeup r/w 0 0:disable mouse wakeup signal (ps_out#) 1:enable mouse wakeup signal 2-1 pwrctrl r/w 11 the acpi control the pson# to 00 : keep last state 10 : always on 01 : bypass mode. 11: always off 0 vsb_pwr_loss r/w 0 when vsb 3v comes, it will set to 1, and write 1 to clear it acpi control register ? index f5h bit name r/w default description 7 sel_s3 r/w 0 kbc s3 signal select 0: kbc enter s3 state if s3# is low (ts3 is 0) or ts3 is set. 1: kbc enter s3 state if vdd3v below 2.5v. 6 reserved - - reserved 5 bypass_lrst r/w 1 0: enable lreset# de-bounce circuit (200us) for pcirst# signal. 1: disable lreset# de-bounce circuit (200us) for pcirst# signal. 4 rstcon_en r/w 0 0: rstcon# asserts via pwrok. 1: rstcon# asserts via pcirst#. 3-2 delay r/w 11 the pwrok delay timing from vcc3vok by following setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms
aug, 2010 v0.12p 36 F71858AD 1 bypass_db r/w 0 bypass the s3#/s4#/psin#/rstin# pins. 0 vindb_en r/w 1 0: disable rstcon# 50ms de-bounce circuit. 1: enable rstcon# 50ms de-bounce circuit. acpi soft reset register ? index f6h bit name r/w default description 7 soft_rst_acpi w 0 software reset to acpi set to 1 to reset acpi 6-0 reserved - - reserved acpi reset enable register ? index f7h bit name r/w default description 7-5 reserved - - reserved 4 pcirst5_en r/w 1 0: disable pcirst5# output. 1: enable pcirst5# output. 3 pcirst4_en r/w 1 0: disable pcirst4# output. 1: enable pcirst4# output. 2 pcirst3_en r/w 1 0: disable pcirst3# output. 1: enable pcirst3# output. 1 pcirst2_en r/w 1 0: disable pcirst2# output. 1: enable pcirst2# output. 0 pcirst1_en r/w 1 0: disable pcirst1# output. 1: enable pcirst1# output. acpi reset data register ? index f8h bit name r/w default description 7-5 reserved - - reserved 4 pcirst5_dat r/w 0 write ?1? to output pcirst5# 2ms low pulse. 3 pcirst4_dat r/w 0 write ?1? to output pcirst4# 2ms low pulse. 2 pcirst3_dat r/w 0 write ?1? to output pcirst3# 2ms low pulse. 1 pcirst2_dat r/w 0 write ?1? to output pcirst2# 2ms low pulse. 0 pcirst1_dat r/w 0 write ?1? to output pcirst1# 2ms low pulse. led s0 status register ? index f9h bit name r/w default description 7 phase r/w 0 when bit 7 is the same of the bit 3, led2 oscillate phase is same with led1. 6 reserved - - reserved 5-4 led2_s0 r/w 2?b11 indicate led2 response when system is in s0 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state 3 phase r/w 0 when bit 7 is same with bit 3, led2 oscillate phase is same with led1. 2 reserved - - reserved
aug, 2010 v0.12p 37 F71858AD 1-0 led1_s0 w 2?b00 indicate led1 response when system in s0 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state led s3/s5 status register ? index fah bit name r/w default description 7-6 led2_s5 r/w 2?b00 indicate led2 response when system in s5 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state 5-4 led2_s3 r/w 2?b01 indicate led2 response when system in s3 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state 3-2 led1_s5 r/w 2?b11 indicate led1 response when system in s5 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state. 1-0 led1_s3 w 2?b01 indicate led1 response when system in s3 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state pwok & ps_on control register ? index fbh bit name r/w default description 7 pwok_dat w 1?b0 write 1 to generate a 250ms low pulse from pwok. 6-5 reserved - - reserved 4 s3_pwok_en r/w 0 0: pwok doesn?t gate with s3#. 1: pwok gate with s3#. 3-2 pwok_delay r/w 0 pwok extra delay. 00: 0ms. 01: 100ms. 10: 200ms. 11: 400ms. 1 wdt_pwok_en r/w 0 0: disable wdtrst# asserts from pwok. 1: enable wdtrst# asserts from pwok. 0 pson_del_en r/w 0 set ?1? to enable delay 4 second to power on. pcirst# level control register ? index fch bit name r/w default description 7-5 reserved - - reserved 4 pcirst5_gate r/w 1 write 0 to force pcirst5# low. 3 pcirst4_gate r/w 1 write 0 to force pcirst4# low. 2 pcirst3_gate r/w 1 write 0 to force pcirst3# low. 1 pcirst2_gate r/w 1 write 0 to force pcirst2# low. 0 pcirst1_gate r/w 1 write 0 to force pcirst1# low.
aug, 2010 v0.12p 38 F71858AD 7.4 hardware monitor registers (index port: 0x295; data port: 0x296) *** cr xx = hardware monitor index xx 7.4.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select kbc device c onfiguration registers. 01h: select pme & acpi device configuration registers. 02h: select hardware monitor dev ice configuration registers. 03h: select gpio device c onfiguration registers. 04h: select wdt device configuration registers. 7.4.2 hardware monitor configuration registers hardware monitor device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 hm_en r/w 1 0: disable hardware monitor. 1: enable hardware monitor. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of hm base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 95h the lsb of hm base address. 7.4.3 hardware moni tor device register configuration register ? index 01h bit name r/w default description 7-3 reserved - - reserved 2 power_down r/w 0 hardware monitor function power down. 1 fan_start r/w 1 set one to enable startup of fan monito ring operations; a zero puts the part in standby mode. 0 v_t_start r/w 1 set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode.
aug, 2010 v0.12p 39 F71858AD configuration register ? index 02h bit name r/w default description 7-6 reserved - - return 0. 5-4 hw_irq_mode r/w 00 00: the hw_irq # will be low active level mode. 01: the hw_irq # will be low active pulse mode. (160us) 10: the hw_irq # will indicate by 1hz led function. 11: the hw_irq # will indicate by (400/800hz) beep output. 4-0 reserved - - -- configuration register ? index 06h bit name r/w default description 7 new_mode_en r/w 0 set this bit to enable new function mode. 6 reserved r 0 reserved 5-4 reserved r/w 0 reserved 3 open_short_sel r / w 0 0: the reading of temperatur e when open will be 0xbb. the reading of temperature when short will be 0xcc. 1: the reading of temperature w hen open or short will be 0x80. 2 reserved r 0 reserved 1-0 dig_rate_sel r/w 0 peci / amd tsi will access the external slave device after 00: diode temperatures convert 1 time. 01: diode temperatures convert 2 times. 10: diode temperatures convert 3 times. 11: diode temperatures convert 4 times. tsi/smbus address register ? index 08h bit name r/w default description 7-1 smbus_addr r/w 7?h26 when amd tsi or intel pch smbus is enabled, this byte is used as smbus_addr. smbus_addr [7:1] is the slave address sent by the embedded master to fetch the temperature. 0 reserved - - reserved peci sst amd tsi interface configuration register ? index 0ah bit name r/w default description 7-6 reserved r/w 0 reserved. 5 t1_iir_en r/w 0 set 1 to enable the iir for amd tsi/peci reading. 4 sst_en r/w 0 enable sst interface. 3-2 peci_power_sel r/w 00 00: peci output high level will be 1.23v 01: peci output high level will be 1.13v 10: peci output high level will be 1.00v 11: peci output high level will be 1.00v 1-0 meas_type r/w 0 select the cpu temperature measure method 00: external thermal diode. 01: peci interface. 10: amd tsi interface. 11: reserved.
aug, 2010 v0.12p 40 F71858AD dual single core select register ? index 0bh (meas_type ==2?b01) bit name r/w default description 7-4 cpu_sel r/w 0 select the intel cpu socket number. 0000: no cpu presented. peci host will use ping() command to find cpu address. 0001: cpu is in socket 0, i.e. peci address is 0x30. 0010: cpu is in socket 1, i.e. peci address is 0x31. 0100: cpu is in socket 2, i.e. peci address is 0x32. 1000: cpu is in socket 3, i.e. peci address is 0x33. others are reserved. 3-2 reserved r 0 reserved 1 tempvalue_sel r/w 0 when dual core cpu selection. tem perature value measurement method will be selected by this bit. 0: average dual cores? temperature. 1: select higher one temper ature of these two cores. 0 dual_core_en r / w 0 when peci interface enable, this will be dual single core select register. 0: single core cpu selection 1: dual core cpu selection tcc activation temperature register ? index 0ch bit name r/w default description 7-0 tcc_temp r/w 0 tcc activation temperature. the absolute value of cpu temperat ure is calculated by the equation if peci or tsi interface is enabled: cpu_temp = tcc_temp + peci reading. cpu_temp = tcc_temp + tsi reading the range of this register is -128 ~ 127. sst address register ? index 0dh bit name r/w default description 7-0 sst_addr r/w 8?h4c address for sst interface. programmable.
aug, 2010 v0.12p 41 F71858AD cpu temp. measure select register ? index 0eh bit name r/w default description 7-4 reserved - 0 reserved. 3 add r/w 0 temperature scale selection. 1: temp. measure = reading value + reading value* 2 -scale[2:0] 0: temp. measure = reading value - reading value* 2 -scale[2:0] 2-0 scale[2:0] r/w 000 when add=1, the temp. measure is 000: 1 * reading value 001: 3/2 * reading value ??.. 110: 65/64 * reading value 111: 129/128 * reading value ------------------------------------------------------------------------- when add=0, the temp. measure is 000: 1 * reading value 001: 1/2 * reading value ??.. 110: 63/64 * reading value 111: 127/128 * reading value peci / amd tsi temp. measure select register ? index 0fh bit name r/w default description 7-4 reserved - 0 reserved. 3 dig_add r/w 0 temperature scale selection. 1: temp. measure = reading value + reading value* 2 -scale[2:0] 0: temp. measure = reading value - reading value* 2 -scale[2:0] 2-0 dig_scale[2:0] r/w 000 when dig_add=1, the temp. measure is 000: 1 * reading value 001: 3/2 * reading value ??.. 110: 65/64 * reading value 111: 129/128 * reading value ------------------------------------------------------------------------- when dig_add=0, the temp. measure is 000: 1 * reading value 001: 1/2 * reading value ??.. 110: 63/64 * reading value 111: 127/128 * reading value *write cr0e will also write cr0f voltage reading and limit ? index 20h- 22h address attribute default description 20h ro -- vcc3v reading. the unit of reading is 8mv. 21h ro -- vsb3v reading. the unit of reading is 8mv. 22h ro -- vbat3v reading. the unit of reading is 8mv.
aug, 2010 v0.12p 42 F71858AD temperature pme# enable register ? index 60h bit name r/w default description 7 reserved r 0 reserved 6 en_t2_high_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit6) 5 en_t1_high_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit5) 4 en_l_high_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit4) 3 reserved r 0 reserved 2 en_ t2_low_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit2) 1 en_ t1_low_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit1) 0 en_l_low_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit0) temperature interrupt status register ? index 61h bit name r/w default description 7 reserved r 0 reserved 6 t2_high_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? set when the temp2 (cr74) exceeds the high limit (cr84) or when temperature return from over high to under low limit (cr85). write 1 to clear this bit, write 0 will be ignored. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp2 (cr74) exceeds the high limit (cr84) or when temperature return from over high to under ?high limit ?hysteresis (cr6d)?. write 1 to clear this bit, write 0 will be ignored. 5 t1_high_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? set when the temp1 (cr72) exceeds the high limit (cr82) or when temperature return from over high to under low limit (cr83). write 1 to clear this bit, write 0 will be ignored. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp1 (cr72) exceeds the high limit (cr82) or when temperature return from over high to under ?high limit ?hysteresis (cr6c)?. write 1 to clear this bit, write 0 will be ignored. 4 local_high_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? set when the local temp (cr70) exceeds the high limit (cr80) or when temperature return from over high to under low limit (cr81). write 1 to clear this bit, write 0 will be ignored. h_l_limit_mode set to 0 (cr69 bit 4) set when the local temp exceeds the high limit (cr80) or when temperature return from over high to under ?high limit ?hysteresis (cr6c)?.. write 1 to clear this bit, write 0 will be ignored. 3 reserved r 0 reserved 2 t2_low_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp2 exceeds the low limit (cr85) or when temperature return from over high to under ?low limit ?hysteresis (cr6d)?.. write 1 to clear this bit, write 0 will be ignored.
aug, 2010 v0.12p 43 F71858AD 1 t1_low_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp1 exceeds the low lim it (cr83) or when temperature return from over high to under ?low limit ?hysteresis (cr6c)?.. write 1 to clear this bit, write 0 will be ignored. 0 local_low_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the local temp exceeds the low limit (cr81) or when temperature return from over high to under ?low limit ?hysteresis (cr6c)?.. write 1 to clear this bit, write 0 will be ignored. temperature real time status register ? index 62h bit name r/w default description 7 reserved r 0 reserved 6 t2_high_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) set when the temp2 exceeds the high limit (cr84). clear when the temp2 is below the low limit (cr85) ?hysteresis (cr6d) temperature. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp2 exceeds the high limit (cr84). clear when the temp2 is below the ?high limit (cr8 4) ?hysteresis (cr6d)? temperature. 5 t1_high_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) set when the temp1 exceeds the high limit (cr82). clear when the temp1 is below the low limit (cr83) ?hysteresis (cr6c) temperature. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp1 exceeds the high limit (cr82). clear when the temp1 is below the ?high limit (cr 82)?hysteresis (cr6c)? temperature. 4 local_high_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) set when the local temp exceeds the high limit (cr80). clear when the local temp is below the low limit (cr81) ?hysteresis (cr6c) temperature. h_l_limit_mode set to 0 (cr69 bit 4) set when the local temp exceeds the high limit (cr80). clear when the local temp is below the ?high limit(cr80)?hysteresis(cr6c)? temperature. 3 reserved r 0 reserved 2 t2_low_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp2 exceeds the low limit (cr85). clear when the temp2 is below the ?low limit(cr85) ?hysteresis (cr6d)? temperature. 1 t1_low_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp1 exceeds the low limit (cr83). clear when the temp1 is below the ?low limit(cr83) ?hysteresis (cr6c)? temperature. 0 local_low_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the local temp exceeds t he low limit (cr81). clear when the local temp is below the ?low limit (cr81)?hysteresis (cr6c)? temperature.
aug, 2010 v0.12p 44 F71858AD cpu exceeds limit temperature select register ? index 64h bit name r/w default description 7-5 reserved r - reserved 4 cpu_temp_sel r/w 0 the diode t1 or peci or amd tsi temperature is used to compare with t1_high_limit/t1_low_limit according to the conditions show below. it is selected by ?new_mode_en? in cr06 [7] and cpu_temp_sel. when {new_mode_en, cpu_temp_sel} is : 0x: select diode t1/peci/amd tsi base on ?meas_type? in cr0a [1:0]. 10: diode t1 is selected 11: select peci or amd tsi base on ?meas_type? in cr0a [1:0]. 3-0 reserved - - reserved hw_irq# output enable register 1 ? index 66h bit name r/w default description 7-3 reserved - - reserved 2 en_t2_ hw_irq r/w 0 when t2_high_exc (cr65 bit6) is active and this bit is enabled. then pin hw_irq# will be active and user can select hw_irq mode from cr 02. 1 en_t1_ hw_irq r/w 1 when t1_high_exc (cr65 bit5) is active and this bit is enabled. then pin hw_irq# will be active and us er can select hw_irq mode from cr02. 0 en_local_hw_ir q r/w 0 when local_high_exc (cr65 bit4) is active and this bit is enabled. then pin hw_irq # will be active and user can select hw_irq mode from cr02. temperature pme# mode and table select register -- index 69h bit name r/w default description 7-5 reserved - - reserved 4 h_l_limit_mode r/w 1 if h_l_limit_mode set to 1 temp exceeds will be set when over high limit. and clear when the temp below the low limit ?hysteresis temperature. else if h_l_limit_mode set to 0 temp exceeds will be set when over high/low limit. and clear when the temp below the ?high/low limit?hysteresis? temperature. 3-0 reserved - - reserved local and temp1 limit hysteresis select register -- index 6ch bit name r/w default description 7-4 temp1_hys r/w 0h temp1 will exceeds when over limit until under then ?limit - temp1_hys (hysteresis)? 3-0 local_hys r/w 0h l temp will exceeds when over limit until under then ?limit ? l temp_hys (hysteresis)? temp2 and temp3 limit hysteresis select register -- index 6dh bit name r/w default description 7-4 reserved - - reserved 3-0 temp2_hys r/w 0h temp2 will exceeds when over limit until under then ?limit ? temp2_hys (hysteresis)?
aug, 2010 v0.12p 45 F71858AD diode open status register -- index 6fh bit name r/w default description 7-4 reserved - - reserved 3 t_dig_open ro 0h open status of peci or tsi interfac e when one of them is enabled. 2 t2_diode_open ro 0h external diode 2 is open or short 1 t1_diode_open ro 0h external diode 1 is open or short 0 t0_diode_open ro 0h internal diode 0 is open or short temperature register ? index 70h- 8fh address attribute default description 70h ro -- local temperature [10:3] readi ng. the unit of reading is 1 o c.at the moment of reading this register. bit10 is the sign bit of the local temperature. maximum display is 127?c, minimum display is -40?c 71h ro -- cr71 bit7-bit5 are the local temperature reading value [2:0]. the unit of reading is 0.125 o c. 72h ro -- temperature 1 [10:3] reading. the unit of reading is 1 o c.at the moment of reading this register. bit10 is the sign bit of t he temperature 1. maximum display is 127?c, minimum display is -40?c (when new_mode_en is set to 1, this byte will always be diode t1 reading) 73h ro -- cr73 bit7-bit5 are the temperature 1 read ing value [2:0]. the unit of reading is 0.125 o c (when new_mode_en is set to 1, this byte will always be diode t1 reading). 74h ro -- temperature 2 [10:3] reading. the unit of reading is 1 o c.at the moment of reading this register. bit10 is the sign bit of t he temperature 2. maximum display is 127?c, minimum display is -40?c 75h ro -- cr75 bit7-bit5 are the temperature 2 readin g value[2:0]. the unit of reading is 0.125 o c. 76-79h ro ffh reserved 7ah ro -- peci or tsi temperature reading 7b~7f ro ffh reserved 80h r/w 46h local temperature sensor high limit. the unit is 1 o c. 81h r/w 3ch local temperature sensor low limit. the unit is 1 o c. 82h r/w 64h temperature sensor 1 high limit. the unit is 1 o c. 83h r/w 55h temperature sensor 1 low limit. the unit is 1 o c. 84h r/w 64h temperature sensor 2 high limit. the unit is 1 o c. 85h r/w 55h temperature sensor 2 low limit. the unit is 1 o c. 86~8dh ro ffh reserved temperature filter select register -- index 8eh bit name r/w default description 7-6 dig-queur r/w 1h the queue time for second filter to quickly update values. 00: 8 times. 01: 16 times. (default). 10: 24 times. 11: 32 times.
aug, 2010 v0.12p 46 F71858AD 5-4 iir-queur2 r/w 1h the queue time for second filter to quickly update values. 00: 8 times. 01: 16 times. (default). 10: 24 times. 11: 32 times. 3-2 iir-queur1 r/w 1h the queue time for second filter to quickly update values. 00: 8 times. 01: 16 times. (default). 10: 24 times. 11: 32 times. 1-0 iir-queur-local r/w 1h the queue time for second filter to quickly update values. 00: 8 times. 01: 16 times. (default). 10: 24 times. 11: 32 times. fan pme# enable register ? index 90h bit name r/w default description 7-3 reserved - - reserved 2 en_fan3_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. (cr91 bit2) 1 en_fan2_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. (cr91 bit1) 0 en_fan1_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. (cr91 bit0) fan interrupt status register ? index 91h bit name r/w default description 7-3 reserved - - reserved 2 fan3_sts r/w -- this bit is set when the fan3 count exce eds the count limit. write 1 to clear this bit, write 0 will be ignored. 1 fan2_sts r/w -- this bit is set when the fan2 count exce eds the count limit. write 1 to clear this bit, write 0 will be ignored. 0 fan1_sts r/w -- this bit is set when the fan1 count exce eds the count limit. write 1 to clear this bit, write 0 will be ignored. fan real time status register ? index 92h bit name r/w default description 7-3 reserved - - reserved 2 fan3_exc ro -- this bit set to high mean that fan3 count can?t meet expect count over than smi time(cr9f) or when duty not ze ro but fan stop over then 3 sec. 1 fan2_exc ro -- this bit set to high mean that fan2 count can?t meet expect count over than smi time(cr9f) or when duty not ze ro but fan stop over then 3 sec. 0 fan1_exc ro -- this bit set to high mean that fan1 count can?t meet expect count over than smi time(cr9f) or when duty not ze ro but fan stop over then 3 sec.
aug, 2010 v0.12p 47 F71858AD fan fault# enable register ? index 93h bit name r/w default description 7 reserved - - reserved 6 full_with_t2_en r/w 0 set one will enable fan to force full speed when t2 over high limit. 5 full_with_t1_en r/w 0 set one will enable fan to force full speed when t1 over high limit. 4 full_with_t0_en r/w 0 set one will enable fan to force full speed when t0 (local temperature) over high limit. 3 reserved ro 0 reserved 2 en_fan3_ hw_irq r/w 0 when fan3_exc (cr92 bit2) is active and this bit is enabled. the pin hw_irq # will be active and user c an select hw_irq mode from cr02. 1 en_fan2_ hw_irq r/w 0 when fan2_exc (cr92 bit1) is active and this bit is enabled. the pin hw_irq # will be active and user c an select hw_irq mode from cr02. 0 en_fan1_ hw_irq r/w 0 when fan1_exc (cr92 bit0) is active and this bit is enabled. the pin hw_irq # will be active and user c an select hw_irq mode from cr02. fan type select register -- index 94h bit name r/w default description 7-6 reserved - - reserved 5-4 fan3_type r/w 1sb 00: output pwm mode (push pull) to control fans. 01: use dac mode application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: use dac mode application circuit to control fan speed by fan?s power terminal. bit 0 default value is trapping by pin fan3_ctrl. if pull up 10k the bit0 default value is 0, else if without pull up resister bit0 default value will be 1(for dac mode) 3-2 fan2_type r/w 1sb 00: output pwm mode (push pull) to control fans. 01: use dac mode application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: use dac mode application circuit to control fan speed by fan?s power terminal. bit 0 default value is trapping by pin fan3_ctrl. if pull up 10k the bit0 default value is 0, else if without pull up resister bit0 default value will be 1(for dac mode) 1-0 fan1_type r/w 1sb 00: output pwm mode (push pull) to control fans. 01: use dac mode application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: use dac mode application circuit to control fan speed by fan?s power terminal. bit 0 default value is trapping by pin fan3_ctrl. if pull up 10k the bit0 default value is 0, else if without pull up resister bit0 default value will be 1(for dac mode) ?s? mean default by trapping. fan mode select register -- index 96h bit name r/w default description 7-6 reserved ro 0h reserved for fan 4
aug, 2010 v0.12p 48 F71858AD 5-4 fan3_mode r/w 1h 00: auto fan speed control, fan spee d will follow different temperature by different rpm that define in 0xc6-0xce. 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle that defined in 0xc6-0xce. 10: manual mode fan control, user can write expect rpm count to 0xc2-0xc3, and F71858AD w ill auto control duty cycle (pwm fan type) or voltage (dac mode type) to control fan speed. 11: manual mode fan control, user can write expect duty to 0xc3, and f71858a will auto control duty cycle (pwm fan type) or voltage (dac mode type) to control fan speed. 3-2 fan2_mode r/w 1h 00: auto fan speed control, fan spee d will follow different temperature by different rpm that define in 0xb6-0xbe. 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle (voltage) that defined in 0xb6-0xbe. 10: manual mode fan control, user can write expect rpm count to 0xb2-0xb3, and F71858AD will auto cont rol duty cycle (pwm fan type) or voltage (dac mode type) to control fan speed. 11: manual mode fan control, user can write expect duty to 0xb3, and f71858a will auto control duty cycle (pwm fan type) or voltage (dac mode type) to control fan speed. 1-0 fan1_mode r/w 1h 00: auto fan speed control, fan spee d will follow different temperature by different rpm that define in 0xa6-0xae. 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle that defined in 0xa6-0xae. 10: manual mode fan control, user can write expect rpm count to 0xa2-0xa3, and F71858AD will auto cont rol duty cycle (pwm fan type) or voltage (dac mode type) to control fan speed. 11: manual mode fan control, user can write expect duty to 0xa3, and f71858a will auto control duty cycle (pwm fan type) or voltage (dac mode type) to control fan speed. auto fan1 and fan2 boundary hystersis select register -- index 98h bit name r/w default description 7-4 fan2_hys r/w 4h boundary hysteresis. (0~15 o c) segment will change when the temperature over the boundary temperature and below the (boun dary temperature? hysteresis). 3-0 fan1_hys r/w 4h boundary hysteresis. (0~15 o c) segment will change when the temperature over the boundary temperature and below the (boundar y temperature ? hysteresis). auto fan3 boundary hystersis select register -- index 99h bit name r/w default description 7-4 reserved - - reserved 3-0 fan3_hys r/w 2h boundary hysteresis. (0~15 o c) segment will change when the temperature over the boundary temperature and below the (boun dary temperature? hysteresis). fan1~fan3 duty change rate select register -- index 9bh (fan_prog_sel = 0 or new_mode_en = 0) bit name r/w default description 7-6 reserved - - reserved
aug, 2010 v0.12p 49 F71858AD 5-4 fan3_rate_sel r/w 1h fan3 duty update rate: 00: 2.5hz 01: 5hz (default) 10: 10hz 11: 20hz 3-2 fan2_rate_sel r/w 1h fan2 duty update rate: 00: 2.5hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_rate_sel r/w 1h fan1 duty update rate: 00: 2.5hz 01: 5hz (default) 10: 10hz 11: 20hz fan1~fan3 duty change rate select register -- index 9bh (fan_prog_sel = 1 or new_mode_en = 0) bit name r/w default description 7-6 reserved - - reserved 5-4 fan3_dn_rate_sel r/w 1h fan3 duty update rate when duty is decreasing: 00: 2.5hz 01: 5hz (default) 10: 10hz 11: 20hz 3-2 fan2_dn_rate_sel r/w 1h fan2 duty update rate when duty is decreasing: 00: 2.5hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_dn_rate_sel r/w 1h fan1 duty update rate when duty is decreasing: 00: 2.5hz 01: 5hz (default) 10: 10hz 11: 20hz fan1 and fan2 start up duty-cycle/voltage ? index 9ch bit name r/w default description 7-4 fan2_min_duty r/w 5h when fan start, the fan_ctrl2 will increase duty-cycle from 0 to this (value x 8) directly. and if fan speed is down, the fan_ctrl 2 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 3-0 fan1_min_duty r/w 5h when fan start, the fan_ctrl 1 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 1 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). fan3 start up duty-cycle/voltage ? index 9dh bit name r/w default description 7-4 reserved - - reserved 3-0 fan3_min_duty r/w 5h when fan start, the fan_ctrl 3 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 3 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4).
aug, 2010 v0.12p 50 F71858AD fan power-on loaded duty-cycle/voltage ? index 9eh bit name r/w default description 7-0 pwron_def_duty r/w 66h when power-on, this duty will be directly loaded to fan1~fan3 for controlling fan. (default duty is 40%) fan fault time register -- index 9fh bit name r/w default description 7 fan_prog_sel r/w 0 select fan_up_rate or fan_dn_rate to be programmed if ?new_mode_en? in cr06 [7] is 1. 6-4 reserved -- -- reserved 3-0 f_fault_time r/w ah this register determines the time of fan fault. the condition to cause fan fault event is: when pwm_duty reaches ffh, if the fan speed count can? t reach the fan expect count in time. the unit of this register is 1 second. the default value is 11 seconds. (set to 0 , means 1 seconds. ; set to 1, means 2 seconds. set to 2, means 3 seconds. ?. ) another condition to cause fan fault event is fan stop and the pwm duty is greater than the minimum duty programmed by the register index 97-98h. fan1 index a0h- afh address attribute default description a0h ro 8?h0f fan1 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a1h ro 8?hff fan1 count reading (lsb). a2h r/w 8?h00 rpm mode(cr96 bit0=0): fan1 expect speed count value (msb), in auto fan mode (cr96 bit1 ? 0) this register is auto updated by hardware. duty mode(cr96 bit0=1): this byte is reserved byte. a3h r/w 8?h01 rpm mode(cr96 bit0=0): fan1 expect speed count value (lsb) or expect pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit0=1): the value programming in this byte is duty value. in auto fan mode(cr96 bit1 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% a4h r/w 8?h03 fan1 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prev ent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a5h r/w 8?hff fan1 full speed count reading (lsb).
aug, 2010 v0.12p 51 F71858AD fan1 boundary 1 temperature ? index a6h bit name r/w default description 7-0 bound1temp1 r/w 46h (70 o c) the 1 st boundary temperature for fan1. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound1temp1[6:0] can be used as 1 st boundary temperature) when fan1 temperature is exceed this boundary, fan1 expect value will load from segment 1 register (index aah). when fan1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 2 register (index abh). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit. fan1 boundary 2 temperature ? index a7h bit name r/w default description 7-0 bound2temp1 r/w 3c (60 o c) the 2 nd boundary temperature for fan1. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound2temp1[6:0] can be used as 2 nd boundary temperature) when fan1 temperature is exceed this boundary, fan1 expect value will load from segment 2 register (index abh). when fan1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 3 register (index ach). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit. fan1 boundary 3 temperature ? index a8h bit name r/w default description 7-0 bound3temp1 r/w 32h (50 o c) the 3 rd boundary temperature for fan1. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound3temp1[6:0] can be used as 3 rd boundary temperature) when fan1 temperature is exceed this boundary, fan1 expect value will load from segment 3 register (index ach). when fan1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 4 register (index adh). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit. fan1 boundary 4 temperature ? index a9h bit name r/w default description 7-0 bound4temp1 r/w 28h (40 o c) the 4 th boundary temperature for fan1. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound4temp1[6:0] can be used as 4 th boundary temperature) when fan1 temperature is exceed this boundary, fan1 expect value will load from segment 4 register (index adh). when fan1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 5 register (index aeh). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit.
aug, 2010 v0.12p 52 F71858AD fan1 segment 1 speed count ? index aah bit name r/w default description 7 - 0 sec1speed1 r / w ffh (100%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: spee e full value 32 32 speed expect ? ? ? ? ? ? + = 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 2 speed count ? index abh bit name r/w default description 7 - 0 sec2speed1 r / w d9h (85%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 3 speed count ? index ach bit name r/w default description 7 - 0 sec3speed1 r / w a6h (65%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 4 speed count ? index adh bit name r/w default description 7 - 0 sec4speed1 r / w 80h (50%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 5 speed count ? index aeh bit name r/w default description 7 - 0 sec5speed1 r / w 66h (40%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
aug, 2010 v0.12p 53 F71858AD fan1 temperature mapping select ? index afh bit name r/w default description 7 fan1_ld_before_en r / w 0 set 1 that fan speed will keep current temp. status before system re-boot up. 6 fan1_no_stop r/w 0 set 1 that fan1 will not stop but keep at fan1_min_duty x 4. 5 fan1_up_t_en r / w 0 set 1 to force fan1 to the highest speed if any temperature over its high limit. 4 fan1_interpolation_en r/w 0 set 1 will enable the interpolati on of the fan expect table. (auto linear mode) 3 fan1_jump_high_en r / w 1 set 1 that fan1 speed will jump to fan1 segment 1 speed when temperature over t1 boundary 1. set 0 that fan1 speed will raise up to fan1 segment 1 speed by slop value( cr9b) when temperature over t1 boundary 1. 2 fan1_jump_low_en r/w 1 set 1 that fan1 speed will jump to fan1 segment 2 speed when temperature under fan1 boundary hystersis. set 0 that fan1 speed will decrease to fan1 segment 2 speed by slop value( cr9b) when temperature under fan1 boundary hystersis. 1-0 fan1_temp_sel r/w 1 0: fan1 follows local temperature 0. 1: fan1 follows temperature 1. 2: fan1 follows temperature 2. 3: fan1 follows peci or tsi tem perature. (when new_mode_en at cr06[7] is set to 1) fan2 index b0h- bfh address attribute default description b0h ro 8?h0f fan2 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b1h ro 8?hff fan2 count reading (lsb). b2h r/w 8?h00 rpm mode(cr96 bit2=0): fan2 expect speed count value (msb), in auto fan mode (cr96 bit3 ? 0) this register is auto updated by hardware. duty mode(cr96 bit2=1): this byte is reserved byte. b3h r/w 8?h01 rpm mode(cr96 bit2=0): fan2 expect speed count value (lsb) or expect pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit2=1): the value programming in this byte is duty value. in auto fan mode (cr96 bit3 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% b4h r/w 8?h03 fan2 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prev ent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b5h r/w 8?hff fan2 full speed count reading (lsb).
aug, 2010 v0.12p 54 F71858AD fan2 boundary 1 temperature ? index b6h bit name r/w default description 7-0 bound1temp2 r/w 46h (70 o c) the 1 st boundary temperature for fan2. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound1temp2[6:0] can be used as 1 st boundary temperature) when fan2 temperature is exceed this boundary, fan2 expect value will load from segment 1 register (index bah). when fan2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 2 register (index bbh). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit. fan2 boundary 2 temperature ? index b7h bit name r/w default description 7-0 bound2temp2 r/w 3c (60 o c) the 2 nd boundary temperature for fan2. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound2temp2[6:0] can be used as 2 nd boundary temperature) when fan2 temperature is exceed this boundary, fan2 expect value will load from segment 2 register (index bbh). when fan2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 3 register (index bch). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit. fan2 boundary 3 temperature ? index b8h bit name r/w default description 7-0 bound3temp2 r/w 32h (50 o c) the 3 rd boundary temperature for fan2. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound3temp2[6:0] can be used as 3 rd boundary temperature) when fan2 temperature is exceed this boundary, fan2 expect value will load from segment 3 register (index bch). when fan2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 4 register (index bdh). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit. fan2 boundary 4 temperature ? index b9h bit name r/w default description 7-0 bound4temp2 r/w 28h (40 o c) the 4 th boundary temperature for fan2. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound4temp2[6:0] can be used as 4 th boundary temperature) when fan2 temperature is exceed this boundary, fan2 expect value will load from segment 4 register (index bdh). when fan2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 5 register (index beh). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit.
aug, 2010 v0.12p 55 F71858AD fan2 segment 1 speed count ? index bah bit name r/w default description 7 - 0 sec1speed2 r / w ffh (100%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. speeed full value 32 32 speed expect ? ? ? ? ? ? + = 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 2 speed count ? index bbh bit name r/w default description 7 - 0 sec2speed2 r / w d9h (85%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 3 speed count ? index bch bit name r/w default description 7 - 0 sec3speed2 r / w a6h (65%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 4 speed count ? index bdh bit name r/w default description 7 - 0 sec4speed2 r / w 80h (50%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 5 speed count ? index beh bit name r/w default description 7 - 0 sec5speed2 r / w 66h (40%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
aug, 2010 v0.12p 56 F71858AD fan2 temperature mapping select ? index bfh bit name r/w default description 7 fan2_ld_before_en r / w 0 set 1 that fan speed will keep current temp. status before system re-boot up. 6 fan2_no_stop r/w 0 set 1 that fan2 will not stop but keep at fan2_min_duty x 4. 5 fan2_up_t_en r / w 0 set 1 to force fan2 to the highest speed if any temperature over its high limit. 4 fan2_interpolation_en r/w 0 set 1 will enable the interpolati on of the fan expect table. (auto linear mode) 3 fan2_jump_high_en r / w 1 set 1 that fan2 speed will jump to fan2 segment 1 speed when temperature over t2 boundary 1. set 0 that fan2 speed will raise up to fan2 segment 1 speed by slope value (cr9b) when temperature over t2 boundary 1. 2 fan2_jump_low_en r/w 1 set 1 that fan2 speed will jump to fan2 segment 2 speed when temperature under fan2 boundary hystersis. set 0 that fan2 speed will decrease to fan2 segment 2 speed by slope value (cr9b) when temperature under fan2 boundary hystersis. 1-0 fan2_temp_sel r/w 2 0: fan2 follows local temperature 0. 1: fan2 follows temperature 1. 2: fan2 follows temperature 2. 3: fan2 follows peci or tsi tem perature. (when new_mode_en at cr06[7] is set to 1) fan3 index c0h- cfh address attribute default description c0h ro 8?h0f fan3 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c1h ro 8?hff fan3 count reading (lsb). c2h r/w 8?h00 rpm mode(cr96 bit4=0): fan3 expect speed count value (msb), in auto fan mode (cr96 bit5 ? 0) this register is auto updated by hardware. duty mode(cr96 bit4=1): this byte is reserved byte. c3h r/w 8?h01 rpm mode(cr96 bit4=0): fan3 expect speed count value (lsb) or expect pwm duty , in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit4=1): the value programming in this byte is duty value. in auto fan mode (cr96 bit5 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% c4h r/w 8?h03 fan3 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prev ent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c5h r/w 8?hff fan3 full speed count reading (lsb).
aug, 2010 v0.12p 57 F71858AD fan3 boundary 1 temperature ? index c6h bit name r/w default description 7-0 bound1temp3 r/w 46h (70 o c) the 1 st boundary temperature for fan3. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound1temp3[6:0] can be used as 1 st boundary temperature) when fan3 temperature is exceed this boundary, fan3 expect value will load from segment 1 register (index cah). when fan3 temperature is below this boundary ? hysteresis, fan3 expect value will load from segment 2 register (index cbh). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit. fan3 boundary 2 temperature ? index c7h bit name r/w default description 7-0 bound2temp3 r/w 3c (60 o c) the 2 nd boundary temperature forfan3. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound2temp3[6:0] can be used as 2 nd boundary temperature) when fan3 temperature is exceed this boundary, fan3 expect value will load from segment 2 register (index cbh). when fan3 temperature is below this boundary ? hysteresis, fan3 expect value will load from segment 3 register (index cch). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit. fan3 boundary 3 temperature ? index c8h bit name r/w default description 7-0 bound3temp3 r/w 32h (50 o c) the 3 rd boundary temperature for fan3. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound3temp3[6:0] can be used as 3 rd boundary temperature) when fan3 temperature is exceed this boundary, fan3 expect value will load from segment 3 register (index cch). when fan3 temperature is below this boundary ? hysteresis, fan3 expect value will load from segment 4 register (index cdh). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit. fan3 boundary 4 temperature ? index c9h bit name r/w default description 7-0 bound4temp3 r/w 28h (40 o c) the 4 th boundary temperature for fan3. (bit7 is sign bit of this boundary temperature. when new_mode_en is not set to 1, only bound4temp3[6:0] can be used as 4 th boundary temperature) when fan3 temperature is exceed this boundary, fan3 expect value will load from segment 4 register (index cdh). when fan3 temperature is below this boundary ? hysteresis, fan3 expect value will load from segment 5 register (index ceh). when new_mode_en at cr06[7] is set to 1, F71858AD will support negative temperature for boundary temperatures. bit 7 of boundary temperatures will be sign bit.
aug, 2010 v0.12p 58 F71858AD fan3 segment 1 speed count ? index cah bit name r/w default description 7 - 0 sec1speed3 r / w ffh (100%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. speeed full value 32 32 speed expect ? ? ? ? ? ? + = 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 2 speed count ? index cbh bit name r/w default description 7 - 0 sec2speed3 r / w d9h (85%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 3 speed count ? index cch bit name r/w default description 7 - 0 sec3speed3 r / w a6h (65%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 4 speed count ? index cdh bit name r/w default description 7 - 0 sec4speed3 r / w 80h (50%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 5 speed count ? index ceh bit name r/w default description 7 - 0 sec5speed3 r / w 66h (40%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
aug, 2010 v0.12p 59 F71858AD fan3 temperature mapping select ? index cfh bit name r/w default description 7 fan3_ld_before_en r / w 0 set 1 that fan speed will keep current temp. status before system re-boot up. 6 fan3_no_stop r/w 0 set 1 that fan3 will not stop but keep at fan3_min_duty x 4. 5 fan3_up_t_en r / w 0 set 1 to force fan3 to the highest speed if any temperature over its high limit. 4 fan3_interpolation_en r/w 0 set 1 will enable the interpolati on of the fan expect table. (auto linear mode) 3 fan3_jump_high_en r / w 1 set 1 that fan3 speed will jump to fan3 segment 1 speed when temperature over t0 boundary 1. set 0 that fan3 speed will raise up to fan3 segment 1 speed by slop value (cr9b) when temperature over t0 boundary 1. 2 fan3_jump_low_en r/w 1 set 1 that fan3 speed will jump to fan3 segment 2 speed when temperature under fan3 boundary hystersis. set 0 that fan3 speed will decrease to fan3 segment 2 speed by slop value (cr9b) when temperature under fan3 boundary hystersis. 1-0 fan3_temp_sel r/w 0 0: fan3 follows local temperature 0. 1: fan3 follows temperature 1. 2: fan3 follows temperature 2. 3: fan3 follows peci or tsi tem perature. (when new_mode_en at cr06[7] is set to 1) fan4 index d0h- d1h address attribute default description d0h ro 8?h0f fan4 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. d1h ro 8?hff fan4 count reading (lsb).
aug, 2010 v0.12p 60 F71858AD 7.5 gpio registers 7.5.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select kbc device c onfiguration registers. 01h: select pme & acpi device configuration registers. 02h: select hardware monitor dev ice configuration registers. 03h: select gpio device c onfiguration registers. 04h: select wdt device configuration registers. 7.5.2 gpio configuration registers gpirq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selgpirq r/w 0h select the irq channel for gpio interrupt. gpio0 output enable register ? index f0h bit name r/w default description 7 gpio07_oe r/w 0 0: gpio07 is in input mode. 1: gpio07 is in output mode. 6 gpio06_oe r/w 0 0: gpio06 is in input mode. 1: gpio06 is in output mode. 5 gpio05_oe r/w 0 0: gpio05 is in input mode. 1: gpio05 is in output mode. 4 gpio04_oe r/w 0 0: gpio04 is in input mode. 1: gpio04 is in output mode. 3 gpio03_oe r/w 0 0: gpio03 is in input mode. 1: gpio03 is in output mode. 2 gpio02_oe r/w 0 0: gpio02 is in input mode. 1: gpio02 is in output mode. this bit is reset by lreset#. 1 gpio01_oe r/w 0 0: gpio01 is in input mode. 1: gpio01 is in output mode. this bit is reset by lreset#. 0 gpio00_oe r/w 0 0: gpio00 is in input mode. 1: gpio00 is in output mode. this bit is reset by lreset#.
aug, 2010 v0.12p 61 F71858AD gpio0 output data register ? index f1h bit name r/w default description 7 gpio07_val r/w 1 0: gpio07 outputs 0 when in output mode. 1: gpio07 outputs1 when in output mode. 6 gpio06_val r/w 1 0: gpio06 outputs 0 when in output mode. 1: gpio06 outputs1 when in output mode. 5 gpio05_val r/w 1 0: gpio05 outputs 0 when in output mode. 1: gpio05 outputs 1 when in output mode. 4 gpio04_val r/w 1 0: gpio04 outputs 0 when in output mode. 1: gpio04 outputs 1 when in output mode. 3 gpio03_val r/w 1 0: gpio03 outputs 0 when in output mode. 1: gpio03 outputs 1 when in output mode. 2 gpio02_val r/w 1 0: gpio02 outputs 0 when in output mode. 1: gpio02 outputs 1 when in output mode. this bit is reset by lreset#. 1 gpio01_val r/w 1 0: gpio01 outputs 0 when in output mode. 1: gpio01 outputs 1 when in output mode. this bit is reset by lreset#. 0 gpio00_val r/w 1 0: gpio00 outputs 0 when in output mode. 1: gpio00 outputs 1 when in output mode. this bit is reset by lreset#. gpio0 pin status register ? index f2h bit name r/w default description 7 gpio07_in r - the pin st atus of led2/gpio07. 6 gpio06_in r - the pin st atus of led1/gpio06. 5 gpio05_in r - the pin stat us of pcirst5#/gpio05. 4 gpio04_in r - the pin stat us of pcirst4#/gpio04. 3 gpio03_in r - the pin st atus of rstin#/gpio03. 2 gpio02_in r - the pin status of fanin4/sst/amdtsi_clk/gpio02. 1 gpio01_in r - the pin st atus of fanin3/gpio01. 0 gpio00_in r - the pin status of peci/amdtsi_data/gpio00. gpio0 drive enable register ? index f3h bit name r/w default description 7 gpio07_drv_en r/w 0 0: gpio07 is open drain in output mode. 1: gpio07 is push pull in output mode. 6 gpio06_drv_en r/w 0 0: gpio06 is open drain in output mode. 1: gpio06 is push pull in output mode. 5 gpio05_drv_en r/w 0 0: gpio05 is open drain in output mode. 1: gpio05 is push pull in output mode. 4 gpio04_drv_en r/w 0 0: gpio04 is open drain in output mode. 1: gpio04 is push pull in output mode. 3 gpio03_drv_en r/w 0 0: gpio03 is open drain in output mode. 1: gpio03 is push pull in output mode.
aug, 2010 v0.12p 62 F71858AD 2 gpio02_drv_en r/w 0 0: gpio02 is open drain in output mode. 1: gpio02 is push pull in output mode. this bit is reset by lreset#. 1 gpio01_drv_en r/w 0 0: gpio01 is open drain in output mode. 1: gpio01 is push pull in output mode. this bit is reset by lreset#. 0 gpio00_drv_en r/w 0 0: gpio00 is open drain in output mode. 1: gpio00 is push pull in output mode. this bit is reset by lreset#. gpio0 pme enable register ? index f4h bit name r/w default description 7 gpio07_pme_en r/w 0 0: disable gpio07 pme. 1: enable gpio07 pme when gpio07_pme_st is set. 6 gpio06_pme_en r/w 0 0: disable gpio06 pme. 1: enable gpio06 pme when gpio06_pme_st is set. 5 gpio05_pme_en r/w 0 0: disable gpio05 pme. 1: enable gpio05 pme when gpio05_pme_st is set. 4 gpio04_pme_en r/w 0 0: disable gpio04 pme. 1: enable gpio04 pme when gpio04_pme_st is set. 3 gpio03_pme_en r/w 0 0: disable gpio03 pme. 1: enable gpio03 pme when gpio03_pme_st is set. 2 gpio02_pme_en r/w 0 0: disable gpio02 pme. 1: enable gpio02 pme when gpio02_pme_st is set. this bit is reset by lreset#. 1 gpio01_pme_en r/w 0 0: disable gpio01 pme. 1: enable gpio01 pme when gpio01_pme_st is set. this bit is reset by lreset#. 0 gpio00_pme_en r/w 0 0: disable gpio00 pme. 1: enable gpio00 pme when gpio00_pme_st is set. this bit is reset by lreset#. gpio0 pme detect select register ? index f5h bit name r/w default description 7 gpio07_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. 6 gpio06_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. 5 gpio05_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. 4 gpio04_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. 3 gpio03_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. 2 gpio02_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. this bit is reset by lreset#.
aug, 2010 v0.12p 63 F71858AD 1 gpio01_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. this bit is reset by lreset#. 0 gpio00_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. this bit is reset by lreset#. gpio0 pme status register ? index f6h bit name r/w default description 7 gpio07_pme_st r/wc 0 0: no gpio07 pme event. 1: a gpio07 pme event is trigger, write ?1? to clear. 6 gpio06_pme_st r/wc 0 0: no gpio07 pme event. 1: a gpio07 pme event is trigger, write ?1? to clear. 5 gpio05_pme_st r/wc 0 0: no gpio07 pme event. 1: a gpio07 pme event is trigger, write ?1? to clear. 4 gpio04_pme_st r/wc 0 0: no gpio07 pme event. 1: a gpio07 pme event is trigger, write ?1? to clear. 3 gpio03_pme_st r/wc 0 0: no gpio07 pme event. 1: a gpio07 pme event is trigger, write ?1? to clear. 2 gpio02_pme_st r/wc 0 0: no gpio07 pme event. 1: a gpio07 pme event is trigger, write ?1? to clear. this bit is reset by lreset#. 1 gpio01_pme_st r/wc 0 0: no gpio07 pme event. 1: a gpio07 pme event is trigger, write ?1? to clear. this bit is reset by lreset#. 0 gpio00_pme_st r/wc 0 0: no gpio07 pme event. 1: a gpio07 pme event is trigger, write ?1? to clear. this bit is reset by lreset#. gpio1 output enable register ? index e0h bit name r/w default description 7-4 reserved - - reserved. 3 gpio13_oe r/w 0 0: gpio13 is in input mode. 1: gpio13 is in output mode. 2 gpio12_oe r/w 0 0: gpio12 is in input mode. 1: gpio12 is in output mode. 1 gpio11_oe r/w 0 0: gpio11 is in input mode. 1: gpio11 is in output mode. 0 gpio10_oe r/w 0 0: gpio10 is in input mode. 1: gpio10 is in output mode. gpio1 output data register ? index e1h bit name r/w default description 7-4 reserved - - reserved. 3 gpio13_val r/w 1 0: gpio13 outputs 0 when in output mode. 1: gpio13 outputs 1 when in output mode.
aug, 2010 v0.12p 64 F71858AD 2 gpio12_val r/w 1 0: gpio12 outputs 0 when in output mode. 1: gpio12 outputs 1 when in output mode. 1 gpio11_val r/w 1 0: gpio11 outputs 0 when in output mode. 1: gpio11 outputs 1 when in output mode. 0 gpio10_val r/w 1 0: gpio10 outputs 0 when in output mode. 1: gpio10 outputs 1 when in output mode. gpio1 pin status register ? index e2h bit name r/w default description 7-4 reserved - - reserved. 3 gpio13_in r - the pin st atus of mdata/gpio13. 2 gpio12_in r - the pin status of mclk/gpio12. 1 gpio11_in r - the pin status of kdata/gpio11. 0 gpio10_in r - the pin status of kclk/gpio10. gpio1 drive enable register ? index e3h bit name r/w default description 7-4 reserved - - reserved. 3 gpio13_drv_en r/w 0 0: gpio13 is open drain in output mode. 1: gpio13 is push pull in output mode. 2 gpio12_drv_en r/w 0 0: gpio12 is open drain in output mode. 1: gpio12 is push pull in output mode. 1 gpio11_drv_en r/w 0 0: gpio11 is open drain in output mode. 1: gpio11 is push pull in output mode. 0 gpio10_drv_en r/w 0 0: gpio10 is open drain in output mode. 1: gpio10 is push pull in output mode. gpio1 pme enable register ? index e4h bit name r/w default description 7-4 reserved - - reserved. 3 gpio13_pme_en r/w 0 0: disable gpio13 pme. 1: enable gpio13 pme when gpio13_pme_st is set. 2 gpio12_pme_en r/w 0 0: disable gpio12 pme. 1: enable gpio12 pme when gpio12_pme_st is set. 1 gpio11_pme_en r/w 0 0: disable gpio11 pme. 1: enable gpio11 pme when gpio11_pme_st is set. 0 gpio10_pme_en r/w 0 0: disable gpio10 pme. 1: enable gpio10 pme when gpio10_pme_st is set. gpio1 pme detect select register ? index e5h bit name r/w default description 7-4 reserved - - reserved. 3 gpio13_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event.
aug, 2010 v0.12p 65 F71858AD 2 gpio12_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. 1 gpio11_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. 0 gpio10_det_sel r/w 0 0: rising edge will trigger a pme event. 1: falling edge will trigger a pme event. gpio1 pme status register ? index e6h bit name r/w default description 7-4 reserved - - reserved. 3 gpio13_pme_st r/wc 0 0: no gpio17 pme event. 1: a gpio17 pme event is trigger, write ?1? to clear. 2 gpio12_pme_st r/wc 0 0: no gpio17 pme event. 1: a gpio17 pme event is trigger, write ?1? to clear. 1 gpio11_pme_st r/wc 0 0: no gpio17 pme event. 1: a gpio17 pme event is trigger, write ?1? to clear. 0 gpio10_pme_st r/wc 0 0: no gpio17 pme event. 1: a gpio17 pme event is trigger, write ?1? to clear. 7.6 wdt registers 7.6.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select kbc device c onfiguration registers. 01h: select pme & acpi device configuration registers. 02h: select hardware monitor dev ice configuration registers. 03h: select gpio device c onfiguration registers. 04h: select wdt device configuration registers. 7.6.2 watchdog confi guration registers wdt device base address enable register ? index 30h bit name r/w default description 7-1 reserved - 0 reserved 0 wdt_en r/w 0 0: disable wdt base address. 1: enable wdt base address.
aug, 2010 v0.12p 66 F71858AD base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of wdt base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 00h the lsb of wdt base address. watchdog control configuration register 1 ? offset + 05h bit name r/w default description 7 reserved r 0 reserved 6 wdtmout_sts r/w 0 if watchdog timeout event occurs, this bit will be set to 1. write a 1 to this bit will clear it to 0. 5 wd_en r/w 0 if this bit is set to 1, the counting of watchdog time is enabled. 4 wd_pulse r/w 0 select output mode (0: level, 1: pulse) of rstout# by setting this bit. 3 wd_unit r/w 0 select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. 2 wd_hactive r/w 0 select output polarity of wdtrst# (1: hi gh active, 0: low acti ve) by setting this bit. 1-0 wd_pswidth r/w 0 select output pulse width of wdtrst# 00: 1 ms 01: 25 ms 10: 125 ms 11: 5 sec watchdog timer configuration register 2 ? offset + 06h bit name r/w default description 7-0 wd_time r/w 0 time of watchdog timer watchdog pme enable configuration register 2 ? offset + 07h bit name r/w default description 7 wdt_pme r -- the pme real time status. this bit will set when wdt_pme_en is set and the watchdog timer is 1 unit before time out (or time out). 6 wdt_pme_en r/w 0 0: disable watchdog pme. 1: enable watchdog pme. 5 wdt_pme_st r/wc - 0: no pme event is trigger. 1: a pme event is trigger, write ?1? to clear. 4 wdout_en r/w 0 0: disable watchdog time out output via pwok. 1: enable watchdog time out output via pwok. 3-0 reserved -- -- reserved.
aug, 2010 v0.12p 67 F71858AD 8. pcb layout guide F71858AD adopts current mode measure method to detect the temperature. this method will not be affected by the different process of cpu via using current mode technology. this technology measures mini-voltage from the remote sensor so a good pcb layout must be needed for noise minimizing. the noises often come from circuit trace which is a track from remote sensor (cpu side) to detect circuit input (F71858AD si de). the signal on this track will be inducted mini-noises when it passes through a high electromagnetic area. those effects will result in the mini-noises and show in the detected side. it will be reported a wrong data which you want to measure. please pay attention and follow up the check list below in order to get an actual and real temperature inside the chip. 1. the d1+/d2+ and agnd (d-) tracks must not pass through/by pwm power-mos. keep as far as possible from power mos. 2. place a 0.1 f bypass capacitor close to the v cc pin. place an external 2200pf input filter capacitors across d+, d- and close to the F71858AD. near the pin agnd (d-) must be placed a through hole into the gnd plane before connect to the external 2200pf capacitor. 3. place the F71858AD as close as practical to the remote sensor diode. in noisy environments, such as a computer main-board, the distance can be 4 to 8 inches. (typ). this length can be increased if the worst noise sources are avoided. noise sources generally include clock generators, crts, memory buses and pci/isa bus etc. 4. separated route the d1+, d2+ with agnd (d-) tracks close together and in parallel after adding external 2200pf capacitor. for more reliable, it had better with grounded guard tracks on each side. provide a ground plane under the tracks if possible. do not route d+ & d- lines next to the deflection coil of the crt. and also don?t route the trace across fast digital signals which can easily induce bigger error. vcc 99 d1+ agnd(d-) 89 86 2200pf f71872f 0.1uf from thermal diode thermda thermdc vcc 99 d1+ agnd(d-) 89 86 2200pf f71872f 0.1uf from thermal diode thermda thermdc F71858AD
aug, 2010 v0.12p 68 F71858AD gnd gnd thermda(dxp) 10mils 10mils minimum 10mils thermdc(dxn) 10mils 5. use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended. 6. try to minimize the number of component/solder joints, called through hole, which can cause thermocouple effects. where through holes are used, make sure that they are in both the d+ and d- path and at the same temperature. thermocouple effects should not be a major problem as 1 corresponds to about 200 v. it means that a copper-solder thermocouple exhibits 3 v/ , and takes about 200 v of the voltage error at d+ & d- to cause a 1 measurement error. adding a few thermocouples causes a negligible error. 7. if the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. it will work up to around 6 to 12 feet. because the measurement technique uses switched current sources, excessive cable and/or filter capacitance will affect the measurement accuracy. when using long cables, the filter capacitor should be reduced or removed. cable resistance can also induce errors. for example: 1 ? series resistance introduces about 0.5 error.
aug, 2010 v0.12p 69 F71858AD 9. electrical characteristics 9.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.0 v input voltage -0.5 to vcc+0.5 v operating temperature 0 to +70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life an d reliability of the device 9.2 dc characteristics (ta = 0 c to 70 c, vcc = 3.3v 10% , vss = 0v ) parameter rating operating voltage 3.0 to 3.6 vcc/vsb operating voltage 2.4 to 3.6 vbat standby current 500ua (typ.) vsb 9.3 dc characteristics continued (ta = 0 c to 70 c, vcc = 3.3v 10%, vss = 0v) parameter sym. min typ max. unit conditions i/o 12t - ttl level bi-directional pin with 12 ma source-sink capability(3.3v) input low voltage vil -0.5 0.8 v input high voltage vih 2.0 vcc+ 0.3 v output low current iol 12 ma 0.4v output high current ioh 12 ma 2.4v input high leakage ilih -1 1 a input low leakage ilil -1 1 a i/ood 16st,5v - ttl level bi-directional pin with 16 ma source-sink capability(3.3v), 5 tolerance input low voltage vil -0.5 0.8 v input high voltage vih 2.0 vcc+ 0.3 v output low current iol 16 ma 0.4v output high current ioh 16 ma 2.4v input high leakage ilih -1 1 a input low leakage ilil -1 1 a i/ood 12st,5v- ttl level bi-directional pin with 12 ma source-sink capability(3.3v), 5 tolerance input low voltage vil -0.5 0.8 v input high voltage vih 2.0 vcc+ 0.3 v
aug, 2010 v0.12p 70 F71858AD output low current iol 12 ma 0.4v output high current ioh 12 ma 2.4v input high leakage ilih -1 1 a input low leakage ilil -1 1 a od 12 ? open-drain output pin with 12ma source-sink capability(3.3v) output low current iol 12 ma 0.4v od 12,5v ? open-drain output pin with12ma sour ce-sink capability(3.3v), 5 tolerance output low current iol 12 ma 0.4v od 16,5v ? open-drain output pin with16ma so urce capability(3.3v), 5v tolerance output low current iol 16 ma 0.4v od 16,u10k ? open-drain output pin with16ma source capability(3.3v), 10k pull high to 3.3v output low current iol 16 ma 0.4v o 16 ? output pin with16ma s ource-sink capability(3.3v) output low current iol 16 ma 0.4v output high current ioh 16 ma 2.4v i lv/ o d8,s1 ? low level bi-directional pin with 8ma source and 1ma sink capability input low voltage vil 0.5 v input high voltage vih 0.9 v output low current iol 1 ma output high current ioh 8 ma 0.75*vtt input high leakage ilih -1 1 a input low leakage ilil -1 1 a i lv/ od 12 ? low level bi-directional pin with 12ma(3.3v)sink capability input low voltage vil 0.5 v input high voltage vih 0.9 v output low current iol 12 ma input high leakage ilih -1 1 a input low leakage ilil -1 1 a i lv/ ood 12 ? low level bi-directional pin with 12ma source-sink(3.3v)capability input low voltage vil 0.5 v input high voltage vih 0.9 v output low current iol 12 ma output high current ioh 12 ma input high leakage ilih -1 1 a input low leakage ilil -1 1 a in lv ? low level input pin input low threshold voltage 0.5 v input hign threshold voltage 0.9 v input high leakage +1 a input low leakage -1 a in st ? ttl level input pin and schmitt trigger input low threshold voltage 0.8 v input hign threshold voltage 2.0 v hysteresis 0.5 v input high leakage +1 a input low leakage -1 a in st,5v ? ttl level input pin and schmitt trigger, 5 tolerance input low threshold voltage 0.8 v input hign threshold voltage 2.0 v hysteresis 0.5 v input high leakage +1 a input low leakage -1 a in t ? ttl level input pin
aug, 2010 v0.12p 71 F71858AD input low threshold voltage 0.8 v input hign threshold voltage 2.0 v input high leakage +1 a input low leakage -1 a in t,5v ? ttl level input pin, 5 tolerance input low threshold voltage 0.8 v input hign threshold voltage 2.0 v input high leakage +1 a input low leakage -1 a 9.4 ac characteristics 9.4.1 ps/2 interface no. description min. max. unit t1 duration of start of receive 5 25 s t2 data valid after falling edge of ps2clk 5 t8 - 5 s t3 ps2dat setup time to falling edge of ps2clk 1 s t4 ps2dat hold time from falling edge of ps2clk 5 95 s t5 duration of inhibit ps/2 device >0 s t6 duration of data frame 2 ms t7 duration of ps2clk inactive 30 50 s t8 duration of ps2clk active 30 50 s t9 duration of ps/2 device inhibit 100 300 s t10 duration of start of transmit 15 ms t11 data valid after falling edge of ps2clk 4 s t12 ps2dat setup time to rising edge of ps2clk 1 s t13 ps2dat hold time from rising edge of ps2clk 5 95 s ps/2 interface timing table data received from ps/2 device ps2clk ps2dat t1 b0 b1 b2 b3 b4 b5 b6 b7 p stop bit start bit t3 t4 t6 1 2 3 4 5 678 910 t7 11 t8 t5 t2 host received from ps/2 interface timing diagram
aug, 2010 v0.12p 72 F71858AD data sent to ps/2 device ps2clk ps2dat t9 t12 b0 b1 b2 b3 b4 b5 b6 b7 p stop bit start bit t11 1 2 3 4 5 678 910 11 t10 t7 t8 t13 ack t6 host send to ps/2 device timing diagram 9.4.2 lpc interface no. description min. max. unit t1 lframe# drive low after rising edge of pciclk 2 12 ns t2 lframe# drive high after rising edge of pciclk 2 12 ns t3 lda[3:0] floating after rising edge of pciclk 28 ns t4 lda[3:0] setup time to rising edge of pciclk 7 ns t5 lda[3:0] hold time from rising edge of pciclk 0 ns t6 period of pciclk 27 33 ns t7 duration of pciclk low 12 ns t8 duration of pciclk high 12 ns lpc interface timing table typical timing for host read pciclk lframe# lad[3:0] start dir addr addr addr addr htar hz sync data data ptar hz t1 t2 t4 t5 t3 0110 0 - i clocks 4 or 8 clocks 2 - 2k clocks 1 - j clocks host read timing diagram
aug, 2010 v0.12p 73 F71858AD typical timing for host write pciclk lframe# lad[3:0] start dir addr addr addr addr htar hz sync data data ptar hz t6 t7 t8 host write timing diagram timing for aboart mechanism pciclk lframe# lad[3:0] start dir addr addr addr addr htar hz sync 0110 0 - i clocks 4 or 8 clocks too many syncs causes timeout sync peripheral must stop driving host will drive high host abort timing diagram 9.4.3 serialized irq interface no. description min. max. unit t1 host drive serirq low after rising edge of pciclk 2 12 ns t2 host drive serirq high after rising edge of pciclk 2 12 ns t3 slave drive serirq low after rising edge of pciclk 2 12 ns t4 slave drive serirq high after rising edge of pciclk 2 12 ns t5 period of pciclk 27 33 ns t6 duration of pciclk low 12 ns t7 duration of pciclk high 12 ns sirq interface timing table
aug, 2010 v0.12p 74 F71858AD start frame timing pciclk serirq drive source t1 t2 4 - 8 clocks start h sl or h r t start frame irq0 frame r t s irq1 frame r t s irq2 frame r t s irq1 host controller none irq1 none h : host control sl : slave control r : recovery t : turn-around s : sample t3 t4 sirq start frame timing diagram stop frame timing pciclk serirq drive source t1 t2 2 or 3 clocks stop hr t stop frame irq14 frame r t s irq15 frame r t s iochck# frame r t s host controller none irq15 h : host control sl : slave control r : recovery t : turn-around s : sample i : idle i next cycl e none 0 - n clocks t5 t6 t7 sirq stop frame timing diagram
aug, 2010 v0.12p 75 F71858AD 10. ordering information part number package type production flow F71858AD 48-lqfp (green package) commercial, 0 c to +70 c version identification: ex: for laa version F71858AD xxxxlaa xxxxxx.xx fintek
aug, 2010 v0.12p 76 F71858AD 11. package dimensions (48lqfp) 2 1 a h d d e b e h e y a a seating plane l l 1 see detail f detail f c 37 48 1 12 13 24 25 36 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 1.40 0.20 0.50 1.00 7.00 9.00 9.00 7.00 --- --- --- 1.60 0.15 1.45 1.35 0.05 0.17 0.27 --- 0.09 0.20 0.45 0.60 0.75 0.08 0 3.5 7 --- --- please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037
F71858AD aug, 2010 v0.12p 77 12. application circuit vcc3v devicerst# atx_pwrgd pwok require to connect to atx_pwrgd pin under "keep last state" function vsb5v lreset# 1 lfram# 2 lad0 3 lad1 4 lad2 5 lad3 6 pciclk 7 serirq 8 vcc 9 peci/amdsi_dat/gpio00 10 fanctl1 11 fanctl2 12 fan_ctl3/wm_dc 13 fanin1 14 fanin2 15 fanin3/gpio01 16 fanin4/sst/amdsi_clk/gpio02 17 ga20 18 kbrst# 19 hw_irq# 20 gnd(d-) 21 d1+ 22 d2+ 23 avcc3v 24 rstin#/gpio03 25 pcirst1# 26 pcirst2# 27 pcirst3# 28 pcirst4#/gpio04 29 pcirst5#/gpio05 30 led1/gpio06 31 led2/gpio07 32 s3gate 33 ps_on# 34 s3# 35 s4# 36 pme# 37 ps_out# 38 ps_in# 39 vsb3v 40 kclk/gpio10 41 kdata/gpio11 42 mclk/gpio12 43 mdata/gpio13 44 gnd 45 pwok 46 rsmrst# 47 vbat 48 u1 F71858AD title size document number rev date: sheet of F71858AD 0.1 F71858AD a 14 friday, july 31, 2009 ovt# kbrst# ga20 iderst# rstin# pwok rsmrat# devicerst# ps_out# ps_in# pme# sled pled peci/amdsi_dat fanctl3 fanctl2 fanctl1 fanin1 fanin3 fanin2 sst/amdsi_clk ga20 kbrst# ovt# d1+ d2+ rstin# iderst# pcirst1# pcirst2# pcirst3# devicerst# s3gate ps_on# s3# s4# pme# ps_out# ps_in# kclk kdata mclk mdata pwok rsmrst# vbat gnd(d-) lreset# lad1 lad0 lfram# lad2 lad3 pciclk serirq 1 2 3 4 5 6 7 8 rp3 4.7k 1 2 3 4 5 6 7 8 rp2 4.7k 1 2 3 4 5 6 7 8 rp1 4.7k pme# ps_out# ovt# iderst# rstin# ps_in# ps_on# rsmrst# vsb3v vcc5v vsb5v vcc3v r1 330 d2 diode d1 diode r2 330 vsb5v pled sled vcc3v c1 0.1u c2 0.1u vsb3v vcc3v d3 diode r3 330
F71858AD aug, 2010 v0.12p 78 amdsi peci sst for system d2+ q1 pnp 3906 d2+ d1+ diode sensing circuit from cpu d1+ gnd(d-) c4 3300p c3 3300p gnd(d-) tit le size document number rev date: sheet of F71858AD 0.1 temperature a 24 friday , july 31, 2009 d- d+ sst/amdsi_clk peci/amdsi_dat host sst client peci 100k amd si_clk si_dat peci/amdsi_dat sst/amdsi_clk 300 300 1.8v
F71858AD aug, 2010 v0.12p 79 1 2 3 4 jp1 4 header 1 2 3 4 jp3 4 header ( 4 pin fa n contr ol) r21 10k vcc5v r28 10k r22 4.7k r25 27k r24 100 +12v + c9 47u c12 0.1u 1 2 d6 1n4148 the c11 is reserv ed f or fan noise dis-bounce. r33 4.7k vcc5v fanin2 fanctl2 r10 4.7k vcc5v r11 4.7k r13 27k r15 10k q2 pnp r7 4.7k +12v r9 4.7k r14 330 1 2 3 jp5 header 3 + c5 47u c7 0.1u q4 mosfet n 2n7002 c16 0.1u r38 10k r36 27k r32 4.7k q7 pnp r31 4.7k r34 4.7k + c13 47u +12v r37 330 q8 mosfet n 2n7002 fanctl1 fanin1 (4 pin fan control) pwm fan 2 speed control pwm fan 3 speed control tit le size document number rev date: sheet of F71858AD 0.1 fan circuit b 34 friday , july 31, 2009 pwm fan 1 speed control r19 3.9k r17 10k dc fan control with op 1 r27 10k 1 2 3 jp4 con3 fanctl2 r30 3.9k r29 10k d7 1n4148 5 6 7 8 4 + - u2b lm358 dc fan control with op 2 fanin2 r26 27k 12v r23 4.7k c10 47u q5 nds0605/sot c11 0.1u d4 1n4148 12v d8 1n4148 q6 nds0605/sot r35 4.7k d9 1n4148 dc fan control with op 3 1 2 3 jp6 con3 12v fanin3 c15 0.1u fanctl3 c14 47u r41 10k r40 10k r42 3.9k r39 27k 3 2 1 8 4 + - u3a lm358 fan control for pwm or dc r20 0 r8 0 q3 nds0605/sot r16 27k 1 2 3 jp2 con3 r18 10k d5 1n4148 r12 4.7k c6 47u c8 0.1u fanctl1 fanctl3 fanin3 fanin1 3 2 1 8 4 + - u2a lm358
F71858AD aug, 2010 v0.12p 80 mc lk r43 4.7k c18 100p md at r44 4.7k f1 fuse c19 0.1u l1 fb l3 fb c17 100p 1 2 3 4 5 6 js1 m-din_6-r r45 4.7k l2 fb 1 2 3 4 5 6 js2 m-din_6-r c20 100p kclk c22 0.1u kdat l4 fb c21 100p f2 fuse r46 4.7k vsb5v tit le size document number rev date: sheet of F71858AD 0.1 kbc a 44 friday , july 31, 2009 ps2 mouse interface ps2 keyboard interface

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